Datasheet

Rev. A | Page 56 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)
1
±1 LSB max ±0.7 LSB typ; differential mode
±1.5 LSB max ±0.9 LSB typ; single-ended and pseudo
differential modes
Differential Nonlinearity (DNL)
1, 3
±0.99 LSB max Differential mode
–0.99/+1.5 LSB max Single-ended and pseudo differential modes
Straight Natural Binary Output Coding
Offset Error
1,2
±7 LSB max
Offset Error Match
1,2
±2 LSB typ
Gain Error
1,2
±2.5 LSB max
Gain Error Match
1,2
±0.5 LSB typ
Twos Complement Output Coding
Positive Gain Error
1,2
±2 LSB max
Positive Gain Error Match
1,2
±0.5 LSB typ
Zero Code Error
1,2
±5 LSB max
Zero Code Error Match
1,2
±1 LSB typ
Negative Gain Error
1,2
±2 LSB max
Negative Gain Error Match
1,2
±0.5 LSB typ
CONVERSION RATE
Conversion Time 14 ADSCLK cycles 437.5 ns with ADSCLK = 32 MHz
Track-and-Hold Acquisition Time
2
90 ns max Full-scale step input; AV
DD
, DV
DD
= 5 V
110 ns max Full-scale step input; AV
DD
, DV
DD
= 3 V
Throughput Rate 2 MSPS max
1
See ADC—Terminology on Page 60.
2
Sample tested during initial release to ensure compliance.
3
Guaranteed no missed codes to 12 bits.
Table 49. Operating Conditions (Power
1
)
Parameter Specification Unit Test Conditions/Comments
POWER SUPPLY REQUIREMENTS
V
DD
2.7/5.25 V min/V max
V
DRIVE
2.7/5.25 V min/V max
I
DD
Digital Logic Inputs = 0 V or V
DRIVE
Normal Mode (Static) 2.3 mA max V
DD
= 5.25 V
Operational
f
S
= 2 MSPS 6.4 mA max V
DD
= 5.25 V; 5.7 mA typ
f
S
= 1.5 MSPS 4 mA max V
DD
= 3.6 V; 3.4 mA typ
Partial Power-Down Mode 500 μA max Static
Full Power-Down Mode (V
DD
)2.8 μA maxStatic
POWER DISSIPATION
Normal Mode (Operational) 33.6 mW max V
DD
= 5.25 V
Partial Power-Down (Static) 2.625 mW max V
DD
= 5.25 V
Full Power-Down (Static) 14.7 μW max V
DD
= 5.25 V
1
In this table, V
DD
refers to both AV
DD
and DV
DD
.
Table 48. Operating Conditions (ADC Performance/Accuracy) (Continued)
Parameter Specification Unit Test Conditions/Comments