Datasheet

Rev. A | Page 48 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
JTAG Test And Emulation Port Timing
Table 42 and Figure 31 describe JTAG port operations.
Table 42. JTAG Port Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
44ns
t
STWI
TWI System Inputs Setup Before TCK High
2
n/a 5 ns
t
HSYS
System Inputs Hold After TCK High
1
55ns
t
TRSTW
TRST Pulse Width
3
(measured in TCK cycles) 4 4 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 10 ns
t
DSYS
System Outputs Delay After TCK Low
4
12 12 ns
1
Applies to System Inputs = PF15–0, PG15–0, PH2–0, NMI, BMODE3–0, RESET.
2
Applies to TWI System Inputs = SCL, SDA. For SDA and SCL system inputs, the system design must comply with V
DDEXT
and VBUSTWI voltages specified for the default
TWI_DT (000) setting in Table 13.
3
50 MHz Maximum
4
System Outputs = EXTCLK, SCL, SDA, PF15–0, PG15–0, PH2–0.
Figure 31. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS