Datasheet

Rev. A | Page 47 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADC Controller Module (ACM) Timing
Table 41 and Figure 30 describe ACM operations.
Note that the ACM clock (ACLK) frequency in MHz is set by
the following equation (in which ACMCKDIV ranges from
0 to 255).
f
ACLK
f
SCLK
2ACMCKDIV×()2+
--------------------------------------------------------
=
t
ACLK
1
f
ACLK
--------------
=
Table 41. ACM Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Units
Timing Requirements
t
SDR
SPORT DRxPRI/DRxSEC Setup Before ACLK 8.0 7.0 ns
t
HDR
SPORT DRxPRI/DRxSEC Hold After ACLK 0 0 ns
Switching Characteristics
t
DO
ACM Controls (ACM_A[2:0], ACM_RANGE, ACM_SGLDIFF) Delay
After Falling Edge of CLKOUT
8.4 8.4 ns
t
DACLK
ACLK Delay After Falling Edge of CLKOUT 4.5 4.5 ns
t
DCS
CS Active Edge Delay After Falling Edge of CLKOUT 5.6 5.3 ns
t
DCSACLK
The Delay Between the Active Edge of CS and the First Edge of
ACLK
t
ACLK
– 5 t
ACLK
– 5 ns
Figure 30. ACM Timing
CS
t
DCSACLK
ACLK
ACM
CONTROLS
DRxPRI/
DRxSEC
CLKOUT
t
DCS
t
DACLK
t
DO
t
SDR
t
HDR