Datasheet

Rev. A | Page 46 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Pulse Width Modulator (PWM) Timing
Table 40 and Figure 29 describe PWM operations.
Table 40. PWM Timing
Parameter Min Max Unit
Timing Requirements
t
ES
External Sync Pulse Width 2 × t
SCLK
+ 1 ns
Switching Characteristics
t
DODIS
Output
1
Inactive (OFF) After Trip Input 12 ns
t
DOE
Output
1
Delay After External Sync
2
2 × t
SCLK
5 × t
SCLK
+ 13 ns
t
OD
Output
1
Delay After Falling Edge of CLKOUT 5 ns
1
PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
2
When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock. For more information, see the ADSP-BF50x Blackfin Processor Hardware Reference.
Figure 29. PWM Timing
PWMx_TRIP
PWMx_SYNC
(AS INPUT)
t
ES
t
DOE
OUTPUT
t
OD
t
DODIS
CLKOUT