Datasheet

Rev. A | Page 45 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Timer Clock Timing
Table 38 and Figure 27 describe timer clock timing.
Up/Down Counter/Rotary Encoder Timing
Table 38. Timer Clock Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High 12.0 12.0 ns
Figure 27. Timer Clock Timing
Table 39. Up/Down Counter/Rotary Encoder Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width t
SCLK
+ 1 t
SCLK
+ 1 ns
t
CIS
Counter Input Setup Time Before CLKOUT High
1
1
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
9.0 7.0 ns
t
CIH
Counter Input Hold Time After CLKOUT High
1
00ns
Figure 28. Up/Down Counter/Rotary Encoder Timing
PPI_CLK
TMRx OUTPUT
t
TODP
CLKOUT
CUD/CDG/CZM
t
CIS
t
CIH
t
WCOUNT