Datasheet

Rev. A | Page 44 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Timer Cycle Timing
Table 37 and Figure 26 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Table 37. Timer Cycle Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
WL
Timer Pulse Width Input Low
(Measured In SCLK Cycles)
1
1 × t
SCLK
1 × t
SCLK
ns
t
WH
Timer Pulse Width Input High
(Measured In SCLK Cycles)
1
1 × t
SCLK
1 × t
SCLK
ns
t
TIS
Timer Input Setup Time Before CLKOUT Low
2
10 8 ns
t
TIH
Timer Input Hold Time After CLKOUT Low
2
–2 –2 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
1 × t
SCLK
– 2.0 (2
32
–1) × t
SCLK
1 × t
SCLK
– 1.5 (2
32
–1) × t
SCLK
ns
t
TOD
Timer Output Update Delay After CLKOUT High 6 6 ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PG0 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 26. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO