Datasheet

Rev. A | Page 38 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Serial Ports
Table 30 through Table 33 on Page 40 and Figure 20 on Page 39
through Figure 22 on Page 40 describe serial port operations.
Table 30. Serial Ports—External Clock
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0 3.0 ns
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0 3.0 ns
t
SDRE
Receive Data Setup Before RSCLKx
1,2
3.0 3.0 ns
t
HDRE
Receive Data Hold After RSCLKx
1,2
3.5 3.0 ns
t
SCLKEW
TSCLKx/RSCLKx Width 4.5 4.5 ns
t
SCLKE
TSCLKx/RSCLKx Period 2 × t
SCLK
2 × t
SCLK
ns
Switching Characteristics
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
10.0 10.0 ns
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
0.0 0.0 ns
t
DDTE
Transmit Data Delay After TSCLKx
3
11.0 10.0 ns
t
HDTE
Transmit Data Hold After TSCLKx
3
0.0 0.0 ns
1
Referenced to sample edge.
2
When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).
3
Referenced to drive edge.
Table 31. Serial Ports—Internal Clock
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0 9.6 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–1.5 –1.5 ns
t
SDRI
Receive Data Setup Before RSCLKx
1,2
11.5 10.0 ns
t
HDRI
Receive Data Hold After RSCLKx
1,2
–1.5 –1.5 ns
Switching Characteristics
t
SCLKIW
TSCLKx/RSCLKx Width 7.0 8.0 ns
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
4.0 3.0 ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
–2.0 –1.0 ns
t
DDTI
Transmit Data Delay After TSCLKx
3
4.0 3.0 ns
t
HDTI
Transmit Data Hold After TSCLKx
3
–1.8 –1.5 ns
1
Referenced to sample edge.
2
When SPORT is used in conjunction with the ACM, refer to the timing requirements in Table 41 (ACM Timing).
3
Referenced to drive edge.