Datasheet

Rev. A | Page 36 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
RSI Controller Timing
Table 28 and Figure 18 describe RSI Controller Timing.
Table 29 and Figure 19 describe RSI controller (high speed)
timing.
Table 28. RSI Controller Timing
Parameter Min Max Unit
Timing Requirements
t
ISU
Input Setup Time 5.75 ns
t
IH
Input Hold Time 2 ns
Switching Characteristics
f
PP
1
Clock Frequency Data Transfer Mode 0 25 MHz
f
OD
Clock Frequency Identification Mode 100
2
400 kHz
t
WL
Clock Low Time 10 ns
t
WH
Clock High Time 10 ns
t
TLH
Clock Rise Time 10 ns
t
THL
Clock Fall Time 10 ns
t
ODLY
Output Delay Time During Data Transfer Mode 14 ns
t
ODLY
Output Delay Time During Identification Mode 50 ns
1
t
PP
= 1/f
PP
2
Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Figure 18. RSI Controller Timing
SD_CLK
INPUT
OUTPUT
t
ISU
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
t
THL
t
TLH
t
WL
t
WH
t
PP
t
IH
t
ODLY
V
OH (MIN)
V
OL (MAX)