Datasheet

Rev. A | Page 33 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Table 25. Clock Out Timing
Parameter
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min Max Unit
Switching Characteristics
t
SCLK
CLKOUT
1
Period
2,3
10 10 ns
t
SCLKH
CLKOUT
1
Width High 44ns
t
SCLKL
CLKOUT
1
Width Low 4 4 ns
1
The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKOUT pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKOUT.
2
The t
SCLK
value is the inverse of the f
SCLK
specification. Reduced supply voltages affect the best-case value of 10 ns listed here.
3
The t
SCLK
value does not account for the effects of jitter.
Figure 11. Clock Out Timing
t
SCLKL
t
SCLKH
t
SCLK
CLKOUT
Table 26. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirements
t
RST _ IN _ PWR
RESET Deasserted after the V
DDINT
, V
DDEXT
, V
DDFLASH
, and CLKIN Pins are Stable and
Within Specification
3500 × t
CKIN
ns
In Figure 12, V
DD_SUPPLIES
is V
DDINT
, V
DDEXT
, and V
DDFLASH
.
Figure 12. Power-Up Reset Timing
RESET
t
RST_IN_PWR
CLKIN
V
DD_SUPPLIES