Datasheet

Rev. A | Page 32 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PROCESSOR—TIMING SPECIFICATIONS
Specifications subject to change without notice.
Clock and Reset Timing
Table 24 and Figure 10 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 14 to
Table 16, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
speed grade. Table 25 and Figure 11 describe clock out timing.
Table 24. Clock and Reset Timing
Parameter Min Max Unit
Timing Requirements
f
CKIN
CLKIN Frequency
1, 2, 3, 4
(Commercial/Industrial Models) 12 50 MHz
CLKIN Frequency
1, 2, 3, 4
(Automotive Models) 14 50 MHz
t
CKINL
CLKIN Low Pulse
1
10 ns
t
CKINH
CLKIN High Pulse
1
10 ns
t
WRST
RESET Asserted Pulse Width Low
5
11 × t
CKIN
ns
Switching Characteristic
t
BUFDLAY
CLKIN to CLKBUF
6
Delay 11 ns
1
Applies to PLL bypass mode and PLL non bypass mode.
2
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 14 on Page 26 through
Table 16 on Page 26.
3
The t
CKIN
period (see Figure 10) equals 1/f
CKIN
.
4
If the DF bit in the PLL_CTL register is set, the minimum f
CKIN
specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
5
Applies after power-up sequence is complete. See Table 26 and Figure 12 for power-up reset timing.
6
The ADSP-BF504/ADSP-BF504F/ADSP-BF506F processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or
CLKOUT. This parameter applies when EXTCLK is programmed to output CLKBUF.
Figure 10. Clock and Reset Timing
CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
t
BUFDLAY
t
BUFDLAY
RESET
CLKBUF