Datasheet

Rev. A | Page 29 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Processor—Electrical Characteristics on Page 27
shows the current dissipation for internal circuitry (V
DDINT
).
I
DDDEEPSLEEP
specifies static power dissipation as a function of
voltage (V
DDINT
) and temperature (see Table 18), and I
DDINT
specifies the total power specification for the listed test condi-
tions, including the dynamic component as a function of voltage
(V
DDINT
) and frequency (Table 19).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories (Table 17).
The ASF is combined with the CCLK Frequency and V
DDINT
dependent data in Table 19 to calculate this part. The second
part is due to transistor switching in the system clock (SCLK)
domain, which is included in the I
DDINT
specification equation.
Table 17. Activity Scaling Factors (ASF)
1
1
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF50x
processors.
I
DDINT
Power Vector Activity Scaling Factor (ASF)
I
DD-PEAK
1.27
I
DD-HIGH
1.24
I
DD-TYP
1.00
I
DD-APP
0.85
I
DD-NOP
0.71
I
DD-IDLE
0.42
Table 18. ADSP-BF50x Static Current — I
DD-DEEPSLEEP
(mA)
T
J
(°C)
1
Voltage (V
DDINT
)
1
1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
–40 1.0 1.0 1.1 1.1 1.2 1.3 1.7 1.9
–20 1.1 1.2 1.3 1.4 1.6 1.7 1.9 2.0
0 1.3 1.4 1.6 1.8 2.0 2.2 2.3 2.5
25 1.9 2.1 2.3 2.5 2.8 3.1 3.3 3.7
40 2.6 2.8 3.0 3.3 3.7 4.0 4.4 4.9
55 3.5 3.8 4.3 4.6 5.0 5.5 6.1 6.7
70 5.0 5.4 6.0 6.4 7.0 7.7 8.4 9.2
85 7.1 7.7 8.3 9.1 9.9 10.8 11.8 12.8
100 10.0 10.8 11.7 12.7 13.7 15.0 16.1 17.5
105 11.1 12.1 13.1 14.2 15.3 16.6 18.0 19.4
1
Valid temperature and voltage ranges are model-specific. See Processor—Operating Conditions on Page 25.
Table 19. ADSP-BF50x Dynamic Current in CCLK Domain (mA, with ASF = 1.0)
1
f
CCLK
(MHz)
2
Voltage (V
DDINT
)
2
1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.40 V 1.45 V 1.50 V
400 N/A N/A N/A N/A 84.46 88.30 92.39 96.35 100.49
350 N/A N/A N/A N/A 74.30 77.93 81.39 84.94 88.61
300 N/A N/A 58.58 61.46 64.49 67.59 70.71 73.76 77.04
250 43.76 46.22 48.64 51.09 53.61 56.19 58.93 61.56 64.22
200 35.26 37.37 39.29 41.33 43.40 45.54 47.79 49.88 52.18
150 26.71 28.38 29.87 31.46 33.09 34.83 36.56 38.22 39.95
100 18.04 19.20 20.25 21.46 22.61 23.83 25.13 26.39 27.72
1
The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Processor—Electrical Characteristics
on Page 27.
2
Valid frequency and voltage ranges are model-specific. See Processor—Operating Conditions on Page 25 and ADSP-BF50x Clock Related Operating Conditions on Page 26.