Datasheet

Rev. A | Page 26 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADSP-BF50x Clock Related Operating Conditions
Table 14 describes the core clock timing requirements for the
ADSP-BF50x processors. Take care in selecting MSEL, SSEL,
and CSEL ratios so as not to exceed the maximum core clock
and system clock (see Table 16). Table 15 describes phase-
locked loop operating conditions.
Table 14. Core Clock (CCLK) Requirements—ADSP-BF50x Processors—All Speed Grades
Parameter Min V
DDINT
Nom V
DDINT
Max CCLK
Frequency Unit
f
CCLK
Core Clock Frequency (All Models) 1.33 V 1.400 V 400 MHz
Core Clock Frequency (Industrial/Commercial Models) 1.16 V 1.225 V 300 MHz
Core Clock Frequency (Industrial Models Only) 1.14 V 1.200 V 200 MHz
Core Clock Frequency (Commercial Models Only) 1.10 V 1.150 V 200 MHz
Table 15. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
72 Instruction Rate
1
MHz
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
84 Instruction Rate
1
MHz
1
For more information, see Ordering Guide on Page 80.
Table 16. Maximum SCLK Conditions for ADSP-BF50x Processors
Parameter V
DDEXT
= 1.8 V/2.5 V/3.3 V Nominal Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
≥ 1.16 V) 100 MHz
CLKOUT/SCLK Frequency (V
DDINT
< 1.16 V) 80 MHz