Datasheet

Rev. A | Page 24 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
D
OUT
A, D
OUT
B O Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked
out on the falling edge of the ADSCLK input and 14 ADSCLKs are required to access the data. The data
simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream
consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first.
If CS
is held low for 16 ADSCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits
of data. If CS
is held low for a further 16 ADSCLK cycles on either D
OUT
A or D
OUT
B, the data from the other
ADC follows on the D
OUT
pin. This allows data from a simultaneous conversion on both ADCs to be
gathered in serial format on either D
OUT
A or D
OUT
B using only one serial port. For more information, see
the ADC—Serial Interface section.
V
DRIVE
P Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the digital I/O
interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than
that at AV
DD
and DV
DD
but should never exceed either by more than 0.3 V.
DV
DD
P Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the internal
ADC. The DV
DD
and AV
DD
voltages should ideally be at the same potential and must not be more than
0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
Table 12. ADC—Signal Descriptions (ADSP-BF506F Processor Only) (Continued)
Signal Name Type Function