Datasheet

Rev. A | Page 22 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
PG14/UA0_RTS/SD_D6/TMR0/PPI_FS1/CUD1 I/O GPIO/UART0 RTS/SD Data 6/Timer0/PPI FS1/Count Up Dir 1 C
PG15/UA0_CTS
/SD_D7/TMR1/PPI_FS2/CDG1 I/O GPIO/UART0 CTS/SD Data 7/Timer1/PPI FS2/Count Down Dir 1 C
Port H: GPIO and Multiplexed Peripherals
PH0/ACM_A2/DT1PRI/SPI0_SEL3
/WAKEUP I/O GPIO/ADCCMA2/SPORT1 TXPriData/SPI0SlaveSelect 3/Wake-up Input C
PH1/ACM_A1/TFS1/SPI1_SEL3
/TACLK3 I/O GPIO/ADCCM A1/SPORT1TXFrameSync/SPI1 SlaveSelect3/AltTimerCLK3 C
PH2/ACM_A0/TSCLK1/SPI1_SEL2
/TACI7 I/O GPIO/ADC CM A0/SPORT1 TX Serial CLK/SPI1 Slave Select 2/Alt Capture In 7 C
TWI (2-Wire Interface) Port
SCL I/O
5V
TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor
value.)
D
SDA I/O
5V
TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2
C specification for the proper resistor
value.)
D
JTAG Port
TCK I JTAG CLK
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
I JTAG Reset
(This signal should be pulled low if the JTAG port is not used.)
EMU
O Emulation Output C
Clock
CLKIN I CLK/Crystal In
XTAL O Crystal Output
EXTCLK O Clock Output B
Mode Controls
RESET
IReset
NMI
I Nonmaskable Interrupt
(This signal should be pulled high when not used.)
BMODE2–0 I Boot Mode Strap 2-0
ADSP-BF50x Voltage Regulation I/F
EXT_WAKE O Wake up Indication C
PG
I Power Good
Power Supplies ALL SUPPLIES MUST BE POWERED
See Processor—Operating Conditions on Page 25.
V
DDEXT
PI/OPowerSupply
V
DDINT
P Internal Power Supply
V
DDFLASH
P Flash Memory Power Supply
GND G Ground for All Supplies
Table 11. Processor—Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type