Datasheet

Rev. A | Page 19 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
is necessary to read from both D
OUT
pins simultaneously.
Figure 7 (ADC (Internal), ACM, and SPORT Connections)
shows both D
OUT
A and D
OUT
B of the ADC connected to one of
the processor’s serial ports. The SPORTx Receive Configuration
1 register and SPORTx Receive Configuration 2 register should
be set up as outlined in Table 9 (The SPORTx Receive Configu-
ration 1 Register (SPORTx_RCR1)) and Table 10 (The SPORTx
Receive Configuration 2 Register (SPORTx_RCR2)).
NOTE: The SPORT must be enabled with the following set-
tings: external clock, external frame sync, and active low frame
sync.
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst. A Blackfin driver for the
ADC is available to download at www.analog.com.
INTERNAL ADC
An ADC is integrated into the ADSP-BF506F product. All ADC
signals are connected out to package pins to enable maximum
interconnect flexibility in mixed signal applications.
The internal ADC is a dual, 12-bit, high speed, low power, suc-
cessive approximation ADC that operates from a single 2.7 V to
5.25 V power supply and features throughput rates up to
2 MSPS. The device contains two ADCs, each preceded by a
3-channel multiplexer, and a low noise, wide bandwidth track-
and-hold amplifier that can handle input frequencies in excess
of 30 MHz.
Figure 8 shows the functional block diagram of the internal
ADC. The ADC features include:
• Dual 12-bit, 3-channel ADC
• Throughput rate: up to 2 MSPS
• Specified for DV
DD
and AV
DD
of 2.7 V to 5.25 V
• Pin-configurable analog inputs
• 12-channel single-ended inputs
or
• 6-channel fully differential inputs
or
• 6-channel pseudo differential inputs
• Accurate on-chip voltage reference: 2.5 V
• Dual conversion with read 437.5 ns, 32 MHz ADSCLK
• High speed serial interface
•SPI-/QSPI
TM
-/MICROWIRE
TM
-/DSP-compatible
• Low power shutdown mode
The conversion process and data acquisition use standard con-
trol inputs allowing easy interfacing to microprocessors or
DSPs. The input signal is sampled on the falling edge of CS
; con-
version is also initiated at this point. The conversion time is
determined by the ADSCLK frequency. There are no pipelined
delays associated with the part.
The internal ADC uses advanced design techniques to achieve
very low power dissipation at high throughput rates. The part
also offers flexible power/throughput rate management when
operating in normal mode as the quiescent current consump-
tion is so low.
The analog input range for the part can be selected to be a 0 V to
V
REF
(or 2 × V
REF
) range, with either straight binary or twos
complement output coding. The internal ADC has an on-chip
2.5 V reference that can be overdriven when an external refer-
ence is preferred.
Table 9. The SPORTx Receive Configuration 1 Register
(SPORTx_RCR1)
Setting Description
RCKFE = 1 Sample data with rising edge of RSCLK
LRFS = 1 Active low frame signal
RFSR = 1 Frame every word
IRFS = 0 External RFS used
RLSBIT = 0 Receive MSB first
RDTYPE = 00 Zero fill
IRCLK = 0 External receive clock
RSPEN = 1 Receive enabled
TFSR = RFSR = 1
Table 10. The SPORTx Receive Configuration 2 Register
(SPORTx_RCR2)
Setting Description
RXSE = 1 Secondary side enabled
SLEN = 1111 16-bit data-word (or may be set to 1101 for
14-bit data-word)
Figure 8. ADC (Internal) Functional Block Diagram
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
D
OUT
A
OUTPUT
DRIVERS
CONTROL
LOGIC
T/H
BUF
V
A1
V
A2
V
A3
V
A4
V
A5
V
A6
MUX
REF
ADC
V
DRIVE
REF SELECT D
CAP
A AV
DD
DV
DD
BUF
D
OUT
B
OUTPUT
DRIVERS
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
V
B1
V
B2
V
B3
V
B4
V
B5
V
B6
MUX
AGND AGND AGND D
CAP
B DGND DGND
CS
ADSCLK
RANGE
SGL/DIFF
A0
A1
A2