Datasheet
For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8 REV. PrA
peripherals can access the DSP’s off-chip boot memory
space. After reset, the DSP always starts executing instruc-
tions from the on-chip boot ROM. Depending on the boot
configuration, the boot ROM code can start booting the
DSP from boot memory. For more information, see Booting
Modes on page 15.
Interrupts
The interrupt controller lets the DSP respond to 17 inter-
rupts with minimum overhead. The controller implements
an interrupt priority scheme as shown in Table 1. Applica-
tions can use the unassigned slots for software and
peripheral interrupts.
Figure 3. ADSP-2196 Memory Map, with On-Chip ROM
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Table 1. Interrupt Priorities/Addresses
Interrupt
IMASK/
IRPTL
Vector
Address
1
Emulator (NMI)—
Highest Priority
NA NA
Reset (NMI) 0 0x00 0000
Power-Down (NMI) 1 0x00 0020
Loop and PC Stack 2 0x00 0040
Emulation Kernel 3 0x00 0060
User Assigned Interrupt 4 0x00 0080
User Assigned Interrupt 5 0x00 00A0
User Assigned Interrupt 6 0x00 00C0
User Assigned Interrupt 7 0x00 00E0
User Assigned Interrupt 8 0x00 0100
User Assigned Interrupt 9 0x00 0120
User Assigned Interrupt 10 0x00 0140
User Assigned Interrupt 11 0x00 0160
User Assigned Interrupt 12 0x00 0180
Table 1. Interrupt Priorities/Addresses (Continued)
Interrupt
IMASK/
IRPTL
Vector
Address
1