Datasheet

This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
53REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196September 2001

The load capacitance should include the processor’s
package capacitance (C
IN
). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2t
CK
). The write strobe can switch every cycle at a
frequency of 1/t
CK
. Select pins switch at 1/(2t
CK
), but selects
can switch on each cycle. For example, estimate P
EXT
with
the following assumptions:
• A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
• One 64K

16 RAM chip is used, each with a load of 10 pF
• Maximum peripheral speed HCLK = 100 MHz
• External data memory writes occur every other cycle, a
rate of 1/(4t
HCLK
), with 50% of the pins switching
• The bus cycle time is 100 MHz (t
HCLK
= 20 nsec)
Figure 29. P
EXT
Calculation
P
EXT
OC
×
V
DD
2
×
f
×
=