Datasheet

This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
51REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196September 2001
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JTAG Test And Emulation Port Timing
Table 22 and Figure 26 describe JTAG port operations.
Table 22. JTAG Port Timing
Parameter Description Min Max Unit
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 4 ns
t
DSYS
System Outputs Delay After TCK Low
1
05ns
Timing Parameters
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 ns
t
SSYS
System Inputs Setup Before TCK Low
2
4ns
t
HSYS
System Inputs Hold After TCK Low
2
5ns
t
TRSTW
TRST Pulsewidth
3
4ns
1
System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,
TFS0, TFS1, RFS0, RFS1, BMS
.
2
System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,
CLKIN, RESET
.
3
50 MHz max.
Figure 26. JTAG Port Timing
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