Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
48 REV. PrA
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Serial Peripheral Interface (SPI) Port—Slave Timing
Table 21 and Figure 24 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter Description Min Max Unit
Switching Characteristics
t
DSOE
SPISS assertion to data out active 06ns
t
DSDHI
SPISS deassertion to data high impedance 06ns
t
DDSPID
SCLK edge to data out valid (data out delay) 0 5 ns
t
HDSPID
SCLK edge to data out invalid (data out hold) 0 5 ns
Timing Requirements
t
SPICHS
Serial clock high period 2t
HCLK
ns
t
SPICLS
Serial clock low period 2t
HCLK
ns
t
SPICLK
Serial clock period 4t
HCLK
ns
t
HDS
Last SPICLK edge to SPISS not asserted 2t
HCLK
ns
t
SPITDS
Sequential Transfer Delay 2t
HCLK
ns
t
SDSCI
SPISS assertion to first SPICLK edge 2t
HCLK
ns
t
SSPID
Data input valid to SCLK edge (data input setup) 1.6 ns
t
HSPID
SCLK sampling edge to data input invalid 1.6 ns