Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
46 REV. PrA

Serial Peripheral Interface (SPI) Port—Master Timing
Table 20 and Figure 23 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter Description Min Max Unit
Switching Characteristics
t
SDSCIM
SPIxSEL low to first SCLK edge (x=0 or 1) 2t
HCLK
ns
t
SPICHM
Serial clock high period 2t
HCLK
ns
t
SPICLM
Serial clock low period 2t
HCLK
ns
t
SPICLK
Serial clock period 4t
HCLK
ns
t
HDSM
Last SCLK edge to SPIxSEL high (x=0 or 1) 2t
HCLK
ns
t
SPITDM
Sequential transfer delay 2t
HCLK
ns
t
DDSPID
SCLK edge to data out valid (data out delay) 0 6 ns
t
HDSPID
SCLK edge to data out invalid (data out hold) 0 5 ns
Timing Requirements
t
SSPID
Data input valid to SCLK edge (data input setup) 1.6 ns
t
HSPID
SCLK sampling edge to data input invalid 1.6 ns