Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
42 REV. PrA
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Serial Port (SPORT) Clocks and Data Timing
Table 18 and Figure 21 describe SPORT transmit and receive operations.
Table 18. Serial Port (SPORT) Clocks and Data Timing
1
1
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed:
1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
Parameter Description Min Max Unit
Switching Characteristics
t
HOFSE
RFS Hold after RCLK (Internally Generated RFS)
2
2
Referenced to drive edge.
012.4ns
t
DFSE
RFS Delay after RCLK (Internally Generated RFS)
2
012.4ns
t
DDTEN
Transmit Data Delay after TCLK
2
012.1ns
t
DDTTE
Data Disable from External TCLK
2
012.0ns
t
DDTIN
Data Enable from Internal TCLK
2
06.8ns
t
DDTTI
Data Disable from Internal TCLK
2
06.3ns
Timing Requirements
t
SCLKIW
TCLK/RCLK Width 20 ns
t
SFSI
TFS/RFS Setup before TCLK/RCLK
3
3
Referenced to sample edge.
–0.6 ns
t
HFSI
TFS/RFS Hold after TCLK/RCLK
3, 4
4
RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from
drive edge.
–0.3 ns
t
SDRI
Receive Data Setup before RCLK
3
–2.3 ns
t
HDRI
Receive Data Hold after RCLK
3
1.9 ns
t
SCLKW
TCLK/RCLK Width 20 ns
t
SFSE
TFS/RFS Setup before TCLK/RCLK
3
–0.6 ns
t
HFSE
TFS/RFS Hold after TCLK/RCLK
3, 4
–0.6 ns
t
SDRE
Receive Data Setup before RCLK
3
–2.2 ns
t
HDRE
Receive Data Hold after RCLK
3
1.8 ns