Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
38 REV. PrA
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Host Port ALE Mode Read Cycle Timing
Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 16. Host Port ALE Mode Read Cycle Timing
Parameter Description Min Max Unit
Switching Characteristics
t
RHKS
HRD asserted to HACK asserted (setup, ACK Mode) 22+t
NH
1
1
t
NH
are peripheral bus latencies (nt
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
the same time.
ns
t
RHKH
HRD de-asserted to HACK de-asserted (hold, ACK Mode) 2ns
t
RHS
HRD asserted to HACK asserted (setup, Ready Mode) 2ns
t
RHH
HRD asserted to HACK de-asserted (hold, Ready Mode) 2+t
NH
1
ns
Timing Requirements
t
CSAL
HCMS or HCIOMS asserted to HALE asserted (delay) 0ns
t
ALCS
HALE de-asserted to optional HCMS or HCIOMS
de-asserted
1ns
t
RCSW
HRD de-asserted to HCMS or HCIOMS de-asserted 1 ns
t
ALR
HALE de-asserted to HRD asserted 1 ns
t
RCS
HRD de-asserted (after last byte) to HCMS or
HCIOMS
de-asserted (ready for next read)
1ns
t
ALPW
HALE asserted pulsewidth 4 ns
t
HKRD
HACK asserted to HRD de-asserted (hold, ACK Mode) 1.5 ns
t
AALS
Address valid to HALE de-asserted (setup) 4 ns
t
ALAH
HALE de-asserted to address invalid (hold) 1 ns
t
RDH
HRD de-asserted to data invalid (hold) 1 ns