Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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Host Port ACC Mode Write Cycle Timing
Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information
on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.
Table 15. Host Port ACC Mode Write Cycle Timing
Parameter Description Min Max Unit
Switching Characteristics
t
WHKS
HWR asserted to HACK asserted (setup, ACK Mode) 0.6 0.6+t
NH
1
1
t
NH
are peripheral bus latencies (nt
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
the same time.
ns
t
WHKH
HWR de-asserted to HACK de-asserted (hold, ACK Mode) 2ns
t
WHS
HWR asserted to HACK asserted (setup, Ready Mode) 0.6 ns
t
WHH
HWR asserted to HACK de-asserted (hold, Ready Mode) 2+t
NH
1
ns
Timing Requirements
t
WAL
HWR asserted to HALE de-asserted (delay) 1.5 ns
t
CSAL
HCMS or HCIOMS asserted to HALE asserted (delay) 0ns
t
ALCS
HALE de-asserted to optional HCMS or HCIOMS
de-asserted
1ns
t
WCSW
HWR de-asserted to HCMS or HCIOMS de-asserted 1 ns
t
ALW
HALE asserted to HWR asserted 0.5 ns
t
CSW
HCMS or HCIOMS asserted to HWR asserted 12ns
t
WCS
HWR de-asserted (after last byte) to HCMS or
HCIOMS
de-asserted (ready for next write)
1ns
t
ALEW
HALE de-asserted to HWR asserted 1 ns
t
HKWD
HACK asserted to HWR de-asserted (hold, ACK Mode) 1.5 ns
t
ADW
Address valid to HWR asserted (setup) 4 ns
t
WAD
HWR de-asserted to address invalid (hold) 1 ns
t
DWS
Data valid to HWR de-asserted (setup) 4 ns
t
WDH
HWR de-asserted to data invalid (hold) 1 ns