Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
32 REV. PrA
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External Port Bus Request and Grant Cycle Timing
Table 13 and Figure 16 describe external port bus request and bus grant operations.
Table 13. External Port Bus Request and Grant Cycle Timing
Parameter Description
1, 2, 3
1
t
HCLK
is the peripheral clock period.
2
These are preliminary timing parameters that are based on worst-case operating conditions.
3
The pad loads for these timing parameters are 20 pF.
Min Max Unit
Switching Characteristics
t
SD
CLKOUT high to xMS, address, and RD/WR disable 4.3 ns
t
SE
CLKOUT low to xMS, address, and RD/WR enable 4.0 ns
t
DBG
CLKOUT high to BG asserted setup 2.2 ns
t
EBG
CLKOUT high to BG de-asserted hold time 2.2 ns
t
DBH
CLKOUT high to BGH asserted setup 2.4 ns
t
EBH
CLKOUT high to BGH de-asserted hold time 2.4 ns
Timing Requirements
t
BS
BR asserted to CLKOUT high setup 4.6 ns
t
BH
CLKOUT high to BR de-asserted hold time 0.0 ns