Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
30 REV. PrA
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External Port Read Cycle Timing
Table 12 and Figure 15 describe external port read operations. For additional information on the ACK signal, see the
discussion on on page 28.
Table 12. External Port Read Cycle Timing
Parameter Description
1, 2, 3
1
t
HCLK
is the peripheral clock period.
2
These are preliminary timing parameters that are based on worst-case operating conditions.
3
The pad loads for these timing parameters are 20 pF.
Min Max Unit
Switching Characteristics
t
CRA
EMI
4
clock low to RD asserted delay
4
EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds
to HCLK (at similar clock ratios).
2.8 ns
t
CSRS
Chip select asserted to RD asserted delay 4.3 6.5 ns
t
ARS
Address valid to RD setup and delay 4.9 7.0 ns
t
AKS
ACK asserted to EMI clock high delay 6.0 ns
t
CRD
EMI clock low to RD de-asserted delay 2.5 2.7 ns
t
RSCS
RD de-asserted to chip select de-asserted setup 4.8 7.0 ns
t
RW
RD strobe pulsewidth t
HCLK
–0.5 ns
t
RSA
RD de-asserted to address invalid setup 4.5 6.6 ns
Timing Requirements
t
AKW
ACK strobe pulsewidth 10.0 ns
t
CDA
RD to data enable access delay 0.0 ns
t
RDA
RD asserted to data access setup t
HCLK
–5.5 ns
t
ADA
Address valid to data access setup t
HCLK
–0.2 ns
t
SDA
Chip select asserted to data access setup t
HCLK
–0.6 ns
t
SD
Data valid to RD de-asserted setup 1.8 ns
t
HRD
RD de-asserted to data invalid hold 0.0 ns