Datasheet

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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
27REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196September 2001
Timer PWM_OUT Cycle Timing
Table 10 and Figure 13 describe timer expired operations. The input signal is asynchronous in “width capture mode” and
has an absolute maximum input frequency of 50 MHz.
Table 10. Timer PWM_OUT Cycle Timing
Parameter Description Min Max Unit
Switching Characteristic
t
HTO
Timer pulsewidth output
1
1
The minimum time for t
HTO
is one cycle, and the maximum time for t
HTO
equals (2
32
–1) cycles.
6.25 (2
32
–1) cycles ns
Figure 13. Timer PWM_OUT Cycle Timing
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