Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
26 REV. PrA
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Programmable Flags Cycle Timing
Table 9 and Figure 12 describe programmable flag operations.
Table 9. Programmable Flags Cycle Timing
Parameter Description Min Max Unit
Switching Characteristic
t
DFO
Flag output delay with respect to HCLK 3 ns
t
HFO
Flag output hold after HCLK high TBD TBD ns
Timing Requirement
t
HFI
Flag input hold is asynchronous 3 ns
Figure 12. Programmable Flags Cycle Timing
FLA G IN PUT
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  
3
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
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3

3

3
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