Datasheet
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
25REV. PrA
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ADSP-2196September 2001
Clock In and Clock Out Cycle Timing
Table 8 and Figure 11 describe clock and reset operations. Per V
DDINT
Internal (Core) Supply Voltage, –0.3 to 3.0 V on
page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.
Table 8. Clock In and Clock Out Cycle Timing
Parameter Description Min Max Unit
Switching Characteristic
t
CKOD
CLKOUT delay from CLKIN 0 5.8 ns
t
CKO
CLKOUT period
1
1
Figure 11 shows a 2 ratio between CLKOUT = 2CLKIN (or t
HCLK
= 2t
CCLK
), but the ratio has many programmable options. For more information
see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference.
10 ns
Timing Requirements
t
CK
CLKIN period
2,3
2
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t
CK
=t
CCLK
.
3
In bypass mode, t
CK
=t
CCLK
.
6.25 200 ns
t
CKL
CLKIN low pulse 2.2 ns
t
CKH
CLKIN high pulse 2.2 ns
t
WRST
RESET asserted pulsewidth low 200t
CLKOUT
ns
t
MSLS
MSELx/BYPASS stable before RESET asserted setup 160 µs
t
MSLH
MSELx/BYPASS stable after RESET de-asserted hold 1000 ns
Figure 11. Clock In and Clock Out Cycle Timing
3
&
&
*'
&
3
%
3
&
3
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3
&
3
3
&
3
3
3