Datasheet
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
23REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196September 2001
I
DD-IDLE2
Supply Current (Core) Idle2 PLL Enabled, HCLK
= 80 MHz, CCLK
Disabled
7
1mA
I
DD-TYPICAL
Supply Current (Core) Typical HCLK = 80 MHz,
CCLK = 160
MHz
7,8
184 mA
I
DD-PEAK
Supply Current (Core) Peak HCLK = 80 MHz,
CCLK = 160
MHz
7,8
215 mA
I
DD-PERIPHERAL1
Supply Current (Peripheral) PLL Enabled, Core,
HCLK Disabled
7
5mA
I
DD-PERIPHERAL2
Supply Current (Peripheral) HCLK = 80 MHz
7
60 mA
I
DD-POWERDOWN
Supply Current PLL, Core, HCLK,
CLKIN Disabled
7
100 µA
C
IN
Input Capacitance
9, 10
f
IN
= 1 MHz,
T
CASE
= 25°C,
V
IN
= 2.5 V
TBD pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,
BG
, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,
RFS2/MOSI1, BMS
, TDO, TXD, EMU.
3
Applies to input pins: ACK, BR, HCMS, HCIOMS, OPMODE, BMODE1–0, HA16, HALE, HRD, HWR, CLKIN, RESET, TCK, TDI, TMS, TRST,
DR0, DR1, BYPASS, RXD.
4
Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.
5
Applies to input pin with internal pull-down: TRST
6
Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU.
7
Test Conditions: @ V
DDINT
= 2.5V, T
AMB
= 25ºC
8
Refer to Table 23 on page 52 for definitions of operation types.
9
Applies to all signal pins.
10
Guaranteed, but not tested.
ELECTRICAL CHARACTERISTICS
(CONTINUED)
Parameter
1
Description Test Conditions Min Typical Max Unit