Datasheet

For current information contact Analog Devices at 800/262-5643
ADSP-2196 September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
12 REV. PrA
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Serial Peripheral Interface (SPI) Ports
The DSP has two SPI-compatible ports that enable the DSP
to communicate with multiple SPI-compatible devices.
These ports are multiplexed with SPORT2, so either
SPORT2 or the SPI ports are active, depending on the state
of the OPMODE pin during hardware reset.
The SPI interface uses three pins for transferring data: two
data pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,
SCKx). Two SPI chip select input pins (SPISSx
) let other
SPI devices select the DSP, and fourteen SPI chip select
output pins (SPIxSEL7–1) let the DSP select other SPI
devices. The SPI select pins are reconfigured Programmable
Flag pins. Using these pins, the SPI ports provide a full
duplex, synchronous serial interface, which supports both
master and slave modes and multimaster environments.
Each SPI port’s baud rate and clock phase/polarities are
programmable (see Figure 4), and each has an integrated
DMA controller, configurable to support both transmit and
receive data streams. The SPI’s DMA controller can only
service unidirectional accesses at any given time.
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
In master mode, the DSP’s core performs the following
sequence to set up and initiate SPI transfers:
1. Enables and configures the SPI port’s operation (data
size, and transfer format).
2. Selects the target SPI slave with an SPIxSELy output
pin (reconfigured Programmable Flag pin).
3. Defines one or more DMA descriptors in Page 0 of I/O
memory space (optional in DMA mode only).
4. Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
5. In non-DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCKx line generates the programmed clock pulses
for simultaneously shifting data out on MOSIx and
shifting data in on MISOx. In DMA mode only, transfers
continue until the SPI DMA word count transitions
from 1 to 0.
In slave mode, the DSP’s core performs the following
sequence to set up the SPI port to receive data from a master
transmitter:
1. Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
2. Defines and generates a receive DMA descriptor in
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
3. Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4. Starts receiving the data on the appropriate SPI SCKx
edges after receiving an SPI chip select on an SPISSx
input pin (reconfigured Programmable Flag pin)
from a master
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. The DSP’s core
could continue, by queuing up the next DMA descriptor.
A slave mode transmit operation is similar, except the DSP’s
core specifies the data buffer in memory space from which
to transmit data, generates and relinquishes control of the
transmit DMA descriptor, and begins filling the SPI port’s
data buffer. If the SPI controller isn’t ready on time to
transmit, it can transmit a “zero” word.
UART Port
The UART port provides a simplified UART interface to
another peripheral or Host. It performs full duplex, asyn-
chronous transfers of serial data. Options for the UART
include support for 5–8 data bits; 1 or 2 stop bits; and none,
even, or odd parity. The UART port supports two modes
of operation:
• PIO (programmed I/O)
The DSP’s core sends or receives data by writing or
reading I/O-mapped UATX or UARX registers, respec-
tively. The data is double-buffered on both transmit and
receive.
• DMA (direct memory access)
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.
The UART’s baud rate (see Figure 5), serial data format,
error code generation and status, and interrupts are
programmable:
• Supported bit rates range from 95 bits to 6.25M bits per
second (100 MHz peripheral clock).
• Supported data formats are 7- or 12-bit frames.
• Transmit and receive status can be configured to generate
maskable interrupts to the DSP’s core.
Figure 4. SPI Clock Rate Calculation
SPI Clock Rate
HCLK
2 SPIBAUD
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