a DSP Microcomputer ADSP-2196 Preliminary Technical Data ADSP-219x DSP CORE FEATURES 6.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 ADSP-2196 DSP FEATURES 16K Words of On-Chip RAM, Configured as 8K Words On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM 16K Words of On-Chip 24-bit ROM Architecture Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals Flexible Power Management with Selectable Power-Down and Idle Modes Programmable PLL Supports 1 to 32 Frequency M
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 TABLE OF CONTENTS ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . 1 ADSP-2196 DSP Features . . . . . . . . . . . . . . . . . . . . . 2 General Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DSP Core Architecture . . .
ADSP-2196 This data sheet provides preliminary information for the ADSP-2196 Digital Signal Processor. GENERAL DESCRIPTION The ADSP-2196 DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
For current information contact Analog Devices at 800/262-5643 Efficient data transfer in the core is achieved with the use of internal buses: Program Memory Address (PMA) Bus Program Memory Data (PMD) Bus Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus DMA Address Bus DMA Data Bus ADSP-2196 " & & )* )* +*' +*' *' *' *' + % % *' & *' Program memory
ADSP-2196 For current information contact Analog Devices at 800/262-5643 a peripheral to one of the 12 user-defined interrupts. These assignments determine the priority of each peripheral for interrupt service. There are three serial ports on the ADSP-2196 that provide a complete synchronous, full-duplex serial interface. This interface includes optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.
September 2001 For current information contact Analog Devices at 800/262-5643 & % '# ( '# '' )) - ADSP-2196 % & ! . % & / . % .
ADSP-2196 September 2001 For current information contact Analog Devices at 800/262-5643 & % '# ( '# '' )) - % & ! . % & / . % .
September 2001 For current information contact Analog Devices at 800/262-5643 Table 1. Interrupt Priorities/Addresses (Continued) 1 ADSP-2196 Table 2.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 PC stack can generate a stack-level interrupt if the PC stack falls below three locations full or rises above 28 locations full. The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK. ENA INT; DIS INT; At reset, interrupt servicing is disabled. For quick servicing of interrupts, a secondary set of DAG and computational registers exist.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 Two mode bits in the Host Port configuration register HPCR [7:6] define the functionality of the HACK line. HPCR6 is initialized at reset based on the values driven on HACK and HACK_P pins (shown in Table 5); HPCR7 is always cleared (0) at reset. HPCR [7:6] can be modified after reset by a write access to the host port configuration register.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 Serial Peripheral Interface (SPI) Ports The DSP has two SPI-compatible ports that enable the DSP to communicate with multiple SPI-compatible devices. These ports are multiplexed with SPORT2, so either SPORT2 or the SPI ports are active, depending on the state of the OPMODE pin during hardware reset.
September 2001 For current information contact Analog Devices at 800/262-5643 HCLK UART Clock Rate = -----------------16 × D Figure 5. UART Clock Rate Calculation1 1 Where D = 1 to 65536 The timers can be used to provide a hardware-assisted autobaud detection mechanism for the UART interface. Programmable Flag (PFx) Pins The ADSP-2196 has 16 bidirectional, general-purpose I/O, Programmable Flag (PF15–0) pins. The PF7–0 pins are dedicated to general-purpose I/O.
ADSP-2196 September 2001 For current information contact Analog Devices at 800/262-5643 • Clear (= 0) the PDWN bit in the PLLCTL register • Set (= 1) the STOPALL bit in the PLLCTL register To exit Power-Down Core/Peripherals mode, the DSP responds to an interrupt and (after five to six cycles of latency) resumes executing instructions with the instruction after the IDLE.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP. The OPMODE, BMODE1, and BMODE0 pins, sampled during hardware reset, and three bits in the Reset Configuration Register implement these modes: The RESET input contains some hysteresis.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 • Boot from SPI, up to 4K bits—The SPI0 port uses the SPI0SEL1 (reconfigured PF2) output pin to select a single serial EPROM device, submits a read command at address 0x00, and begins clocking consecutive data into internal or external memory. Use only SPI-compatible EPROMs of ≤ 4K bit (12-bit address range).
September 2001 For current information contact Analog Devices at 800/262-5643 tor, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. Two key points for these tools are: • Compiled ADSP-219x C/C++ code efficiency—the compiler has been developed for efficient translation of C/C++ code to ADSP-219x assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 As can be seen in Figure 7, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 Table 7.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Table 7.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 Table 7.
ADSP-2196 SPECIFICATIONS For current information contact Analog Devices at 800/262-5643 September 2001 RECOMMENDED OPERATING CONDITIONS Parameter Description1 Min Max Unit VDDINT Internal (Core) Supply Voltage 2.37 2.63 V VDDEXT External (I/O) Supply Voltage TBD 3.6 V VIH1 High Level Input Voltage2, @ VDDINT = max 2.0 VDDEXT V VIH2 High Level Input Voltage3, @ VDDINT = max 2.2 VDDEXT V VIL Low Level Input Voltage2, @ VDDINT = min –0.3 0.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter1 Description Test Conditions IDD-IDLE2 Supply Current (Core) Idle2 IDD-TYPICAL Min Typical Max Unit PLL Enabled, HCLK = 80 MHz, CCLK Disabled7 1 mA Supply Current (Core) Typical HCLK = 80 MHz, CCLK = 160 MHz7,8 184 mA IDD-PEAK Supply Current (Core) Peak HCLK = 80 MHz, CCLK = 160 MHz7,8 215 mA IDD-PERIPHERAL1 Supply Curren
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 ABSOLUTE MAXIMUM RATINGS VDDINTInternal (Core) Supply Voltage1,2 .......–0.3 to 3.0 V VDDEXTExternal (I/O) Supply Voltage ............–0.3 to 4.6 V VIL–VIHInput Voltage ......................–0.5 to VDDEXT +0.5 V VOL–VOHOutput Voltage Swing ........–0.5 to VDDEXT +0.5 V CLLoad Capacitance............................................ 200 pF tCCLKCore Clock Period...............................
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 Clock In and Clock Out Cycle Timing Table 8 and Figure 11 describe clock and reset operations. Per VDDINTInternal (Core) Supply Voltage, –0.3 to 3.0 V on page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz. Table 8. Clock In and Clock Out Cycle Timing Parameter Description Min Max Unit 5.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Programmable Flags Cycle Timing Table 9 and Figure 12 describe programmable flag operations. Table 9.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 Timer PWM_OUT Cycle Timing Table 10 and Figure 13 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an absolute maximum input frequency of 50 MHz. Table 10. Timer PWM_OUT Cycle Timing Parameter Description Min Max Unit 6.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 External Port Write Cycle Timing Table 11 and Figure 14 describe external port write operations. The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 & 3 % 3 % 3 3 & 3% % *' * ' 3% % 3 % 3% % 3 &% & 3 3 3 % 3 % )* ' Figure 14. External Port Write Cycle Timing REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 External Port Read Cycle Timing Table 12 and Figure 15 describe external port read operations. For additional information on the ACK signal, see the discussion on on page 28. Table 12. External Port Read Cycle Timing Parameter Description1, 2, 3 Min Max Unit 2.8 ns Switching Characteristics tCRA EMI4 clock low to RD asserted delay tCSRS Chip select asserted to RD asserted delay 4.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 & 3 3 3 & 3 3 * ' *' 3 % 3 3 3 &% & 3 3 3 )*' 3 3 3 Figure 15. External Port Read Cycle Timing REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 External Port Bus Request and Grant Cycle Timing Table 13 and Figure 16 describe external port bus request and bus grant operations. Table 13. External Port Bus Request and Grant Cycle Timing Parameter Description1, 2, 3 Min Max Unit Switching Characteristics tSD CLKOUT high to xMS, address, and RD/WR disable 4.3 ns tSE CLKOUT low to xMS, address, and RD/WR enable 4.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 & 3 3 3 3 3 3 3 3 *' *' % 3 3 3 3 Figure 16. External Port Bus Request and Grant Cycle Timing REV. PrA This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Host Port ALE Mode Write Cycle Timing Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10. Table 14. Host Port ALE Mode Write Cycle Timing Parameter Description Min Max Unit 0.6 0.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 3 3 % 3 3% % % 3% 3 % % 3% 3 &% & 3% & & & 3% & & 3% & 3 % 3 )* ' 3 3% ( ( ( % ( ! % Figure 17. Host Port ALE Mode Write Cycle Timing REV.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Host Port ACC Mode Write Cycle Timing Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10. Table 15. Host Port ACC Mode Write Cycle Timing Parameter Description Min Max Unit 0.6 0.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 3 3 3% % 3% 3 % 3 % 3 % 3 &% 3% % 3% 3% & & & & 3% )*' 3% & & 3% & 3 % 3 % 3% ( ( ( % ( ! % Figure 18. Host Port ACC Mode Write Cycle Timing REV.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Host Port ALE Mode Read Cycle Timing Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10. Table 16.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 3 3 % 3 3 % 3 3 3 3 & & 3 & & & 3 & 3 & & & 3 3 3 )* ' ( ( ( % ( ! % Figure 19. Host Port ALE Mode Read Cycle TIming REV.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Host Port ACC Mode Read Cycle Timing Table 17 and Figure 20 describe host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10. Table 17.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 3 3 3 3% % 3 % 3 % 3 3 3 3 & & 3 & & & 3 3 3% 3 % & & )* ' & & 3 ( ( ( % ( ! % Figure 20.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Serial Port (SPORT) Clocks and Data Timing Table 18 and Figure 21 describe SPORT transmit and receive operations. Table 18. Serial Port (SPORT) Clocks and Data Timing1 Parameter Description Min Max Unit Switching Characteristics tHOFSE RFS Hold after RCLK (Internally Generated RFS)2 0 12.4 ns tDFSE RFS Delay after RCLK (Internally Generated RFS)2 0 12.
September 2001 & 3 ( & % & 3 ADSP-2196 For current information contact Analog Devices at 800/262-5643 4 ( 3 3 3 4 ! 3 & &% & 3 3 3 3 3 3 3 3 1 & & !
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Serial Port (SPORT) Frame Synch Timing Table 19 and Figure 22 describe SPORT frame synch operations. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) R/TCLK width. Table 19.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 ! ( ( % 5 - 5 ' ( & 3 3 3 3 3 3 ( ! ( & 3 3 3 3 3 3 Figure 22.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Serial Peripheral Interface (SPI) Port—Master Timing Table 20 and Figure 23 describe SPI port master operations. Table 20.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 # # 5 ' 6 7 3 3 3 3 3 & 3 & 5 ' 3 3 & 5 3 3 5 3 3 3 ( 5' 3 3 3 ( (
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Serial Peripheral Interface (SPI) Port—Slave Timing Table 21 and Figure 24 describe SPI port slave operations. Table 21.
September 2001 ADSP-2196 For current information contact Analog Devices at 800/262-5643 3 3 3 & 5 3 3 3 & 3 3 3 3 3 ( 3 3 ( 3 5' 3 ( 3 3 5 3 3 3 3
ADSP-2196 For current information contact Analog Devices at 800/262-5643 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 25 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 25 there is some latency between the generation September 2001 internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 JTAG Test And Emulation Port Timing Table 22 and Figure 26 describe JTAG port operations. Table 22.
ADSP-2196 September 2001 For current information contact Analog Devices at 800/262-5643 Output Drive Currents ' Figure 27 shows typical I-V characteristics for the output drivers of the ADSP-2196. The curves represent the current drive capability of the output drivers as a function of output voltage.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 2 P EXT = O × C × V DD × f Figure 29. PEXT Calculation The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK.
For current information contact Analog Devices at 800/262-5643 September 2001 ADSP-2196 The PEXT equation is calculated for each class of pins that can drive as shown in Table 24. Table 24. PEXT Calculation Pin Type # of Pins % Switching C f VDD2 = PEXT Address 15 50 TBD pF 25.0 MHz 10.9 V =TBD W MSx 1 0 TBD pF 25.0 MHz 10.9 V =TBD W WR 1 — TBD pF 25 MHz 10.9 V =TBD W Data 16 50 TBD pF 25.0 MHz 10.
September 2001 For current information contact Analog Devices at 800/262-5643 0.4 V. CL is the total bus capacitance (per data line), .)( and IL .)( is the total leakage or three-state current (per data line). The hold time will be Figure 34. Voltage Reference Levels for AC t DECAY plus the minimum Measurements Enable/Disable) Output (Except : .)( disable time (i.e., tDATRWH for the write cycle). )'; Figure 33.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 .) *<= '. * . - '> *"'> .' .) .' .) .' '.) ' ' ' ' ' ' '' ' ' *; ' ' '' Figure 36. Typical Output Rise Time (10%-90%, VDDEXT =Min) vs. Load Capacitance ) *<= * ) )' +) '' ) )' *; +) '' Figure 37.
ADSP-2196 1 For current information contact Analog Devices at 800/262-5643 September 2001 These are preliminary estimates. 57 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. REV.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 ADSP-2196 144-Lead LQFP Pinout Table 26 lists the LQFP pinout by signal name. Table 26. 144-Lead LQFP Pins (Alphabetically By Signal) SIGNAL PIN # A0 84 A1 85 A2 86 A3 87 A4 88 A5 89 A6 91 A7 92 A8 93 A9 95 A10 96 A11 97 A12 98 A13 99 A14 101 A15 102 A16 103 A17 104 A18 106 A19 107 A20 108 A21 109 ACK 120 BG 111 BGH 110 BMODE0 70 58 Table 26.
ADSP-2196 SIGNAL PIN # TRST 79 53 VDDEXT 13 VDDEXT 25 VDDEXT 40 VDDEXT 63 VDDEXT VDDEXT VDDEXT VDDEXT 90 100 118 131 VDDEXT 143 VDDINT 19 VDDINT 58 VDDINT 82 VDDINT GND GND GND 127 5 16 29 GND 33 GND 54 GND 55 GND 77 GND GND GND GND 80 94 105 129 GND 134 WR 121 59 For current information contact Analog Devices at 800/262-5643 Table 26.
ADSP-2196 For current information contact Analog Devices at 800/262-5643 September 2001 Table 27.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 Table 27. 144-Lead LQFP Pins (Numerically By Pin Number (Continued) SIGNAL PIN # MS3 119 ACK 120 WR 121 RD 122 D0 123 D1 124 D2 125 D3 126 VDDINT 127 D4 128 GND 129 CLKOUT 130 VDDEXT 131 CLKIN 132 XTAL 133 GND 134 D5 135 D6 136 D7 137 D8 138 D9 139 D10 140 D11 141 D12 142 VDDEXT 143 D13 144 REV.
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 144-Lead Mini-BGA Pinout Table 28 lists the mini-BGA pinout by signal name. Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) Table 28.
September 2001 For current information contact Analog Devices at 800/262-5643 Table 28. 144-Lead Mini-BGA Pins (Alphabetically By Signal) (Continued) Table 28.
September 2001 BALL # VDDINT D6 VDDINT F4 VDDINT G9 VDDINT J7 VDDEXT E5 VDDEXT E6 VDDEXT F5 VDDEXT F6 VDDEXT G7 VDDEXT G8 VDDEXT H7 VDDEXT H8 GND A1 GND A12 GND E7 GND F7 GND F8 GND F9 GND G4 GND G5 GND G6 GND H5 GND L6 GND M1 GND M12 WR C8 XTAL B6 REV. PrA For current information contact Analog Devices at 800/262-5643 Table 28.
September 2001 For current information contact Analog Devices at 800/262-5643 Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) Table 29.
September 2001 For current information contact Analog Devices at 800/262-5643 Table 29. 144-Lead Mini-BGA Pins (Numerically By Ball Number) (Continued) Table 29.
For current information contact Analog Devices at 800/262-5643 September 2001 ADSP-2196 OUTLINE DIMENSIONS . 144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144) .'' . ' ! $ '.'' '.+) '. ' '. ) $ '" ' '. + '. '. + ( % % + '.' ! + + '. ) '.') . ) . ' . ) '.)' 1 . . .
September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2196 ORDERING GUIDE Part Number1, 2 Ambient Temperature Range Instruction Rate On-Chip SRAM Operating Voltage ADSP-2196MKST-160X 0ºC to 70ºC 160 MHz 1.3M bit 2.5 Int./3.3 Ext. V ADSP-2196MBST-140X 140 MHz 1.3M bit 2.5 Int./3.3 Ext. V ADSP-2196MKCA-160X 0ºC to 70ºC 160 MHz 1.3M bit 2.5 Int./3.3 Ext. V ADSP-2196MBCA-140X -40ºC to 85ºC 140 MHz 1.3M bit 2.5 Int./3.3 Ext.
