Datasheet

ADSP-2191M
–34– REV. A
Figure 18. Serial Ports
DT
DT
t
DDTTE
t
DDTEN
t
DDTTI
t
DDTIN
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK/RCLK
TCLK (EXT)
TFS (“LATE,” EXT.)
t
SDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRI
t
SFSI
t
HFSI
t
DFSE
t
HOFSE
t
SCLKIW
DATA RECEIVE-INTERNAL CLOCK
t
SDRE
DATA RECEIVE-EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTI
t
HDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSI
t
HFSI
t
SCLKIW
t
DFSE
t
HOFSE
DATA TRANSMIT-INTERNAL CLOCK
t
DDTE
t
HDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DATA TRANSMIT-EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK (INT)
TFS (“LATE,” INT.)