Datasheet

ADSP-2191M
–22– REV. A
External Port Write Cycle Timing
Table 12 and Figure 11 describe external port write operations.
The external port lets systems extend read/write accesses in three
ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising
edge of EMI clock. ACK low causes the DSP to wait, and the
DSP requires two EMI clock cycles after ACK goes high to finish
the access. For more information, see the External Port chapter
in the
ADSP-219x/ADSP-2191 DSP Hardware Reference .
Table 12. External Port Write Cycle Timing
Parameter
1, 2
Min Max Unit
Switching Characteristics
t
CSWS
Chip Select Asserted to WR Asserted Delay 0.5t
HCLK
–4 ns
t
AWS
Address Valid to WR Setup and Delay 0.5t
HCLK
–3 ns
t
WSCS
WR Deasserted to Chip Select Deasserted 0.5t
HCLK
–4 ns
t
WSA
WR Deasserted to Address Invalid 0.5t
HCLK
–3 ns
t
WW
WR Strobe Pulsewidth t
HCLK
–2+W
3
ns
t
CDA
WR to Data Enable Access Delay 0ns
t
CDD
WR to Data Disable Access Delay 0.5t
HCLK
–3 0.5t
HCLK
+4 ns
t
DSW
Data Valid to WR Deasserted Setup t
HCLK
+1+W
3
t
HCLK
+7+W
3
ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC
4
3.4 ns
t
DHW
WR Deasserted to Data Invalid Hold Time; E_WHC
4
t
HCLK
+3.4 ns
t
WWR
WR Deasserted to WR, RD Asserted t
HCLK
Timing Requirements
t
AKW
ACK Strobe Pulsewidth 12.5 ns
t
DWSAK
ACK Delay from WR Low 0 ns
1
t
HCLK
is the peripheral clock period.
2
These are timing parameters that are based on worst-case operating conditions.
3
W = (number of waitstates specified in wait register) ⴛ t
HCLK.
4
Write hold cycle–memory select control registers (MS ⴛ CTL).
Figure 11. External Port Write Cycle Timing
D15–0
t
AWS
t
WW
t
AKW
t
DHW
t
CDD
ACK
WR
A21–0
MS 3–0
IO MS
BMS
t
CSWS
t
WSA
t
WSCS
t
CDA
t
DWSAK
RD
t
DSW
t
WWR