Datasheet

–15–REV. A
ADSP-2191M
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the
EE-68:
Analog Devices
J TAG Emulation Technical Reference on the Analog
Devices website (www.analog.com)—use site search on
“EE-68.” This document is updated regularly to keep pace with
improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-2191M
architecture and functionality. For detailed information on the
core architecture of the ADSP-219x family, refer to the
ADSP-219x/ADSP-2191 DSP Hardware Reference . For details on
the instruction set, refer to the
ADSP-219x Instruction Set
Reference
.
PIN FUNCTION DESCRIPTIONS
ADSP-2191M pin definitions are listed in Table 7. All
ADSP-2191M inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for
TRST ).
Tie or pull unused inputs to V
DDEXT
or GND, except for
ADDR21–0, DATA15–0, PF7-0, and inputs that have internal
pull-up or pull-down resistors (
TRST , BMODE0, BMODE1,
OPMODE, BYPASS, TCK, TMS, TDI, and
RESET )—these
pins can be left floating. These pins have a logic-level hold circuit
that prevents input from floating internally.
The following symbols appear in the Type column of Table 7: G
= Ground, I = Input, O = Output, P = Power Supply, and T =
Three-State.
Figure 7. JTAG Pod Connector Keep-Out Area
0.10"
0.1 5"
Table 7. Pin Function Descriptions
Pin Type Function
A21–0 O/T External Port Address Bus
D7–0 I/O/T External Port Data Bus, least significant 8 bits
D15
/PF15
/SPI1SEL7
I/O/T
I/O
I
Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave
Select output 7 (if 8-bit external bus, when SPI1 enabled)
D14
/PF14
/SPI0SEL7
I/O/T
I/O
I
Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave
Select output 7 (if 8-bit external bus, when SPI0 enabled)
D13
/PF12
/SPI1SEL6
I/O/T
I/O
I
Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave
Select output 6 (if 8-bit external bus, when SPI1 enabled)
D12
/PF12
/SPI0SEL6
I/O/T
I/O
I
Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave
Select output 6 (if 8-bit external bus, when SPI0 enabled)
D11
/PF11
/SPI1SEL5
I/O/T
I/O
I
Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave
Select output 5 (if 8-bit external bus, when SPI1 enabled)
D10
/PF10
/SPI0SEL5
I/O/T
I/O
I
Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave
Select output 5 (if 8-bit external bus, when SPI0 enabled)
D9
/PF9
/SPI1SEL4
I/O/T
I/O
I
Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select
output 4 (if 8-bit external bus, when SPI1 enabled)
D8
/PF8
/SPI0SEL4
I/O/T
I/O
I
Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select
output 4 (if 8-bit external bus, when SPI0 enabled)
PF7
/SPI1SEL3
/DF
I/O/T
I
I
Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency
(divisor select for PLL input during boot)
PF6
/SPI0SEL3
/MSEL6
I/O/T
I
I
Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6
(during boot)