Datasheet

–37–REV. A
ADSP-2191M
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 21 and Figure 22 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter Min Max Unit
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active 08ns
t
DSDHI
SPISS Deassertion to Data High Impedance 010ns
t
DDSPID
SCLK Edge to Data Out Valid (Data Out Delay) 0 10 ns
t
HDSPID
SCLK Edge to Data Out Invalid (Data Out Hold) 0 10 ns
Timing Requirements
t
SPICHS
Serial Clock High Period 2t
HCLK
ns
t
SPICLS
Serial Clock Low Period 2t
HCLK
ns
t
SPICLK
Serial Clock Period 4t
HCLK
ns
t
HDS
Last SPICLK Edge to SPISS Not Asserted 2t
HCLK
ns
t
SPITDS
Sequential Transfer Delay 2t
HCLK
+4 ns
t
SDSCI
SPISS Assertion to First SPICLK Edge 2t
HCLK
ns
t
SSPID
Data Input Valid to SCLK Edge (Data Input Setup) 1.6 ns
t
HSPID
SCLK Sampling Edge to Data Input Invalid (Data In Hold) 2.4 ns
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
t
HSPID
t
DDSPID
t
DSDHI
LSBMSB
MSB
VALID
t
HSPID
t
DSOE
t
HDSPID
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPID
SPISS
(INPUT)
SCLK
(CPOL = 0)
(INPUT)
SCLK
(CPOL = 1)
(INPUT)
t
SDSCI
t
SPICHS
t
SPICLS
t
SPICLS
t
SPICLK
t
HDS
t
SPIC HS
t
SSPID
t
HSPID
t
DSDHI
LSB
VALID
MSB
MSB
VALID
t
DSOE
t
DDSPID
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPID
LSB
VALID
LSB
t
SPITDS
CPHA = 0
CPHA = 1
t
DDSPID