Datasheet

ADSP-2191M
–36– REV. A
Serial Peripheral Interface (SPI) Port—Master Timing
Table 20 and Figure 21 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter Min Max Unit
Switching Characteristics
t
SDSCIM
SPIxSEL Low to First SCLK edge (x=0 or 1) 2t
HCLK
–3 ns
t
SPICHM
Serial Clock High Period 2t
HCLK
–3 ns
t
SPICLM
Serial Clock Low Period 2t
HCLK
–3 ns
t
SPICLK
Serial Clock Period 4t
HCLK
–1 ns
t
HDSM
Last SCLK Edge to SPIxSEL High (x=0 or 1) 2t
HCLK
–3 ns
t
SPITDM
Sequential Transfer Delay 2t
HCLK
–2 ns
t
DDSPID
SCLK Edge to Data Output Valid (Data Out Delay) 0 6 ns
t
HDSPID
SCLK Edge to Data Output Invalid (Data Out Hold) 0 5 ns
Timing Requirements
t
SSPID
Data Input Valid to SCLK Edge (Data Input Setup) 8 ns
t
HSPID
SCLK Sampling Edge to Data Input Invalid (Data In Hold) 1 ns
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
t
HSPID
t
HDSPID
LSBMSB
t
HSPID
t
DDSPID
MOSI
(OUTPUT)
MISO
(INPUT)
SPIxSEL
(O UTPUT)
(x = 0 or 1)
SCLK
(CPOL = 0)
(OUTPUT)
SCLK
(CPOL = 1)
(OUT PUT)
t
SPICHM
t
SPICLM
t
SPICLM
t
SPICLK
t
SPICHM
t
HDSM
t
SPITDM
t
HDSPID
LSB
VALID
LSBMSB
MSB
VALID
t
HSPID
t
DDSPID
MOSI
(OUTPUT)
MISO
(INPUT)
t
SSPID
CPHA = 0
MSB
VALID
t
SDSCIM
t
SSPID
LSB
VALID
CPHA = 1
t
SSPID