Datasheet

–35–REV. A
ADSP-2191M
Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5t
SCLK
)
Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5t
HCLK
)
DRIVE
SAMPLE
DRIVE
t
DTENLFSE
t
DDTLFSE
EXTERNAL RFS WITH MCE = 1, MFD = 0
1ST BIT 2ND BIT
DT
RCLK
RFS
LATE EXTERNAL TFS
t
HDTE /I
t
DDTE / I
t
SFSE/ I
DRIVE
SAMPLE
DRIVE
t
DTENLFSE
t
DDTLFSE
1ST BIT 2ND BIT
DT
TCLK
TFS
t
HDTE / I
t
DDTE /I
t
HOSFSE/ I
t
HOSFSE/ I
t
SFSE/ I
t
DDTLFSE
DRIVE
SAMPLE
DRIVE
t
DTENLFSE
t
DDTLFSE
EXTERNAL RFS WITH MCE = 1, MFD = 0
1ST BIT 2ND BIT
DT
RCLK
RFS
LATE EXTERNAL TFS
t
HDTE / I
t
DDTE /I
t
SFSE/ I
DRIVE
SAMPLE
DRIVE
t
DTENLFSE
1ST BIT 2ND BIT
DT
TCLK
TFS
t
HDTE / I
t
DDTE / I
t
HOFSE/ I
t
HOFSE/ I
t
SFSE/ I