Datasheet

–33–REV. A
ADSP-2191M
Serial Ports
Table 19 and Figure 18 describe SPORT transmit and receive
operations, while Figure 19 and Figure 20 describe SPORT
Frame Sync operations.
Table 19. Serial Ports
1, 2
Parameter Min Max Unit
External Clock Timing Requirements
t
SFSE
TFS/RFS Setup Before TCLK/RCLK
3
4ns
t
HFSE
TFS/RFS Hold After TCLK/RCLK
3
4ns
t
SDRE
Receive Data Setup Before RCLK
3
1.5 ns
t
HDRE
Receive Data Hold After RCLK
3
4ns
t
SCLKW
TCLK/RCLK Width 0.5t
HCLK
–1 ns
t
SCLK
TCLK/RCLK Period 2t
HCLK
ns
Internal Clock Timing Requirements
t
SFSI
TFS Setup Before TCLK
4
; RFS Setup Before RCLK
3
4ns
t
HFSI
TFS/RFS Hold After TCLK/RCLK
3
3ns
t
SDRI
Receive Data Setup Before RCLK
3
2ns
t
HDRI
Receive Data Hold After RCLK
3
5ns
External or Internal Clock Switching Characteristics
t
DFSE
TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)
4
14 ns
t
HOFSE
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)
4
3ns
External Clock Switching Characteristics
t
DDTE
Transmit Data Delay After TCLK
4
13.4 ns
t
HDTE
Transmit Data Hold After TCLK
4
4ns
Internal Clock Switching Characteristics
t
DDTI
Transmit Data Delay After TCLK
4
13.4 ns
t
HDTI
Transmit Data Hold After TCLK
4
4ns
t
SCLKIW
TCLK/RCLK Width 0.5t
HCLK
–3.5 0.5t
HCLK
+2.5 ns
Enable and Three-State
5
Switching Characteristics
t
DTENE
Data Enable from External TCLK
4
012.1ns
t
DDTTE
Data Disable from External TCLK
4
13 ns
t
DTENI
Data Enable from Internal TCLK
4
013ns
t
DDTTI
Data Disable from External TCLK
4
12 ns
External Late Frame Sync Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS with MCE=1, MFD=0
6, 7
10.5 ns
t
DTENLFSE
Data Enable from Late FS or MCE=1, MFD = 0
6, 7
3.5 ns
1
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay
and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2
Word selected timing for I
2
S mode is the same as TFS/RFS timing (normal framing only).
3
Referenced to sample edge.
4
Referenced to drive edge.
5
Only applies to SPORT0/1.
6
MCE=1, TFS enable, and TFS valid follow t
DDTENFS
and t
DDTLFSE
.
7
If external RFSD/TFS setup to RCLK/TCLK >0.5t
LSCK
, t
DDTLSCK
and t
DTENLSCK
apply; otherwise t
DDTLFSE
and t
DTENLFS
apply.