Datasheet

–31–REV. A
ADSP-2191M
Host Port ACC Mode Read Cycle Timing
Table 18 and Figure 17 describe Host port read operations in
Address Cycle Control (ACC) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description on Page 8.
Table 18. Host Port ACC Mode Read Cycle Timing
Parameter Min Max Unit
Switching Characteristics
t
RHKS1
HRD Asserted to HACK Asserted (ACK Mode) First Byte 12t
HCLK
15t
HCLK
+t
NH
1
ns
t
RHKS2
HRD Asserted to HACK Asserted (Setup, ACK Mode)
2
10 ns
t
RHKH
HRD Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns
t
RHS
HRD Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
t
RHH
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
12t
HCLK
15t
HCLK
+t
NH
1
ns
t
RDH
HRD Deasserted to Data Invalid (Hold) 1 ns
t
WSHKS
HWR Asserted to HACK Asserted (Setup) During Address
Latch
10 ns
t
WHHKH
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
10 ns
t
RDD
HRD Deasserted to Data Disable 10 ns
Timing Requirements
t
CSAL
HCMS or HCIOMS Asserted to HALE Asserted (Delay) 0ns
t
ALCS
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
1ns
t
RCSW
HRD Deasserted to HCMS or HCIOMS Deasserted 0 ns
t
ALW
HALE Asserted to HWR Asserted 0.5 ns
t
ALER
HALE Deasserted to HWR Asserted 1 ns
t
CSR
HCMS or HCIOMS Asserted to HRD Asserted 0ns
t
RCS
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
0ns
t
WAL
HWR Deasserted to HALE Deasserted (Delay) 2.5 ns
t
HKRD
HACK Asserted to HRD Deasserted (Hold, ACK Mode) 1.5 ns
t
ADW
Address Valid to HWR Deasserted (Setup) 2 ns
t
WAD
HWR Deasserted to Address Invalid (Hold) 1 ns
t
HKWAL
HACK Asserted to HWR Deasserted (Hold) During Address
Latch
2
2ns
1
t
NH
are peripheral bus latencies (n ⴛt
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
the same time.
2
Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).