Datasheet

–25–REV. A
ADSP-2191M
Host Port ALE Mode Write Cycle Timing
Table 15 and Figure 14 describe Host port write operations in
Address Latch Enable (ALE) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description on Page 8.
Table 15. Host Port ALE Mode Write Cycle Timing
Parameter Min Max Unit
Switching Characteristics
t
WHKS1
HWR Asserted to HACK Asserted (Setup, ACK Mode) First
Byte
10 5t
HCLK
+t
NH
1
ns
t
WHKS2
HWR Asserted to HACK Asserted (Setup, ACK Mode)
2
10 ns
t
WHKH
HWR Deasserted to HACK Deasserted (Hold, ACK Mode) 10 ns
t
WHS
HWR Asserted to HACK Asserted (Setup, Ready Mode) 10 ns
t
WHH
HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
05t
HCLK
+t
NH
1
ns
Timing Requirements
t
CSAL
HCMS or HCIOMS Asserted to HALE Asserted 0ns
t
ALPW
HALE Asserted Pulsewidth 4 ns
t
ALCSW
HALE Deasserted to HCMS or HCIOMS Deasserted 1 ns
t
WCSW
HWR Deasserted to HCMS or HCIOMS Deasserted 0 ns
t
ALW
HALE Deasserted to HWR Asserted 1 ns
t
WCS
HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)
0ns
t
HKWD
HACK Asserted to HWR Deasserted (Hold, ACK Mode) 1.5 ns
t
AALS
Address Valid to HALE Deasserted (Setup) 2 ns
t
ALAH
HALE Deasserted to Address Invalid (Hold) 4 ns
t
DWS
Data Valid to HWR Deasserted (Setup) 4 ns
t
WDH
HWR Deasserted to Data Invalid (Hold) 1 ns
1
t
NH
are peripheral bus latencies (nⴛt
HCLK
); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory
at the same time.
2
Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).