Datasheet

ADSP-2191M
–24– REV. A
External Port Bus Request and Grant Cycle Timing
Table 14 and Figure 13 describe external port bus request and
bus grant operations.
Table 14. External Port Bus Request and Grant Cycle Timing
Parameter
1, 2
Min Max Unit
Switching Characteristics
t
SD
CLKOUT High to xMS, Address, and RD/WR Disable 0.5t
HCLK
+1 ns
t
SE
CLKOUT Low to xMS, Address, and RD/WR Enable04ns
t
DBG
CLKOUT High to BG Asserted Setup 0 4 ns
t
EBG
CLKOUT High to BG Deasserted Hold Time 0 4 ns
t
DBH
CLKOUT High to BGH Asserted Setup 0 4 ns
t
EBH
CLKOUT High to BGH Deasserted Hold Time04ns
Timing Requirements
t
BS
BR Asserted to CLKOUT High Setup 4.6 ns
t
BH
CLKOUT High to BR Deasserted Hold Time 0 ns
1
t
HCLK
is the peripheral clock period.
2
These are timing parameters that are based on worst-case operating conditions.
Figure 13. External Port Bus Request and Grant Cycle Timing
t
BH
A21–0
CLKOUT
t
BS
t
SD
t
SD
t
SD
t
DBG
t
DBH
t
SE
t
SE
t
SE
t
EBG
t
EBH
BGH
WR
RD
MS3--0
IOMS
BMS
BR
BG