Datasheet

–23–REV. A
ADSP-2191M
External Port Read Cycle Timing
Table 13 and Figure 12 describe external port read operations.
For additional information on the ACK signal, see the discussion
on Page 22.
Table 13. External Port Read Cycle Timing
Parameter
1, 2
Min Max Unit
Switching Characteristics
t
CSRS
Chip Select Asserted to RD Asserted Delay 0.5t
HCLK
–3 ns
t
ARS
Address Valid to RD Setup and Delay 0.5t
HCLK
–3 ns
t
RSCS
RD Deasserted to Chip Select Deasserted Setup 0.5t
HCLK
–2 ns
t
RW
RD Strobe Pulsewidth t
HCLK
–2+W
3
ns
t
RSA
RD Deasserted to Address Invalid Setup 0.5t
HCLK
–2 ns
t
RWR
RD Deasserted to WR, RD Asserted t
HCLK
Timing Requirements
t
AKW
ACK Strobe Pulsewidth t
HCLK
ns
t
RDA
RD Asserted to Data Access Setup t
HCLK
–4+W
3
ns
t
ADA
Address Valid to Data Access Setup t
HCLK
+W
3
ns
t
SDA
Chip Select Asserted to Data Access Setup t
HCLK
+W
3
ns
t
SD
Data Valid to RD Deasserted Setup 7 ns
t
HRD
RD Deasserted to Data Invalid Hold 0 ns
t
DRSAK
ACK Delay from RD Low 0 ns
1
t
HCLK
is the peripheral clock period.
2
These are timing parameters that are based on worst-case operating conditions.
3
W = (number of waitstates specified in wait register) ⴛ t
HCLK
.
Figure 12. External Port Read Cycle Timing
D15–0
t
ARS
t
RW
t
AKW
t
CDA
t
RDA
t
ADA
t
SDA
t
SD
t
HRD
ACK
RD
A21–0
t
CSRS
t
RSA
t
RSCS
t
DRSAK
t
RWR
MS3--0
IOMS
BMS
WR