Datasheet

–21–REV. A
ADSP-2191M
Programmable Flags Cycle Timing
Table 10 and Figure 9 describe Programmable Flag operations.
Timer PWM_OUT Cycle Timing
Table 11 and Figure 10 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and has
an absolute maximum input frequency of 40 MHz.
Table 10. Programmable Flags Cycle Timing
Parameter Min Max Unit
Switching Characteristics
t
DFO
Flag Output Delay with Respect to CLKOUT 7 ns
t
HFO
Flag Output Hold After CLKOUT High 6 ns
Timing Requirement
t
HFI
Flag Input Hold is Asynchronous 3 ns
Figure 9. Programmable Flags Cycle Timing
PF
(INPUT)
t
HFI
PF
(OUTPUT)
CLKOUT
FLAG INPUT
t
DFO
t
HFO
FLAG OUTPUT
Table 11. Timer PWM_OUT Cycle Timing
Parameter Min Max Unit
Switching Characteristic
t
HTO
Timer Pulsewidth Output
1
12.5 (2
32
–1) cycles ns
1
The minimum time for t
HTO
is one cycle, and the maximum time for t
HTO
equals (2
32
–1) cycles.
Figure 10. Timer PWM_OUT Cycle Timing
HCLK
PWM_OUT
t
HTO