Datasheet

ADSP-2191M
–20– REV. A
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s external
signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, parameters
cannot be added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its
signals. No control is possible over this timing; circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics indicate what the
processor will do in a given circumstance. Switching character-
istics can also be used to ensure that any timing requirement of
a device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation.Timing requirements guarantee that the
processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
Table 9 and Figure 8 describe clock and reset operations. Com-
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160/80 MHz for commercial
grade and 140/70 MHz for industrial grade, when the peripheral
clock rate is one-half the core clock rate. If the peripheral clock
rate is equal to the core clock rate, the maximum peripheral clock
rate is 80 MHz for both commercial and industrial grade parts.
The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing
Parameter Min Max Unit
Switching Characteristics
t
CKOD
CLKOUT Delay from CLKIN 0 5.8 ns
t
CKO
CLKOUT Period
1
12.5 ns
Timing Requirements
t
CK
CLKIN Period
2, 3
10 200 ns
t
CKL
CLKIN Low Pulse 4.5 ns
t
CKH
CLKIN High Pulse 4.5 ns
t
WRST
RESET Asserted Pulsewidth Low 200t
CLKOUT
ns
t
MSS
MSELx/BYPASS Stable Before RESET Deasserted Setup 40 µs
t
MSH
MSELx/BYPASS Stable After RESET Deasserted Hold 1000 ns
t
MSD
MSELx/BYPASS Stable After RESET Asserted 200 ns
t
PFD
Flag Output Disable Time After RESET Asserted 10 ns
1
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
2
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t
CK
= t
CCLK
.
3
In bypass mode, t
CK
= t
CCLK
.
Figure 8. Clock In and Clock Out Cycle Timing
t
CKOD
CLKOUT
MSEL6–0
BYPASS
DF
RESET
CLKIN
t
WRST
t
CDD
t
CK
t
CKL
t
MSH
t
CKO
t
PFD
t
MSD
t
MSS