Datasheet

ADSP-2191M
–2– REV. A
INTEGRATION FEATURES
160K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM
Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-Bit
Accumulators
Unified Memory Space Allows Flexible Address Genera-
tion, Using Two Independent DAG Units
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Enhanced Interrupt Controller Enables Programming of
Interrupt Priorities and Nesting Modes
SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit
Host Interface
16-Bit External Memory Interface for up to 16M Words of
Addressable Memory Space
Three Full-Duplex Multichannel Serial Ports, with
Support for H.100 and up to 128 TDM Channels with
A-Law and ␮-Law Companding Optimized for Telecom-
munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Interrupt
Support
Three Programmable Interval Timers with PWM
Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time
for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External
8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection
Programmable PLL Supports 1ⴛ to 32ⴛ Input Frequency
Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .8
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . .9
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . .19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Environmental Conditions . . . . . . . . . . . . . . . . . . . .41
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .43
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .45
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48