Datasheet
–19–REV. A
ADSP-2191M
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Power Dissipation
Using the operation-versus-current information in Table 8, designers can estimate the ADSP-2191M’s internal power supply (V
DDINT
)
input current for a specific application, according to the formula for I
DDINT
calculation beneath Table 8. For calculation of external
supply current and total supply current, see Power Dissipation on Page 40.
V
DDINT
Internal (Core) Supply Voltage
1
. . . –0.3 V to +3.0 V
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
V
DDEXT
External (I/O) Supply Voltage . . . . –0.3 V to +4.6 V
V
IL
–V
IH
Input Voltage . . . . . . . . . . –0.5 V to V
DDEXT
+0.5 V
V
OL
–V
OH
Output Voltage Swing. . . –0.5 V to V
DDEXT
+0.5 V
T
STORE
Storage Temperature Range. . . . . .–65ºC to +150ºC
T
LEAD
Lead Temperature of ST-144 (5 seconds) . . . . 185ºC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
Table 8. Operation Types Versus Input Current
K-Grade
I
DDINT
(mA) CCLK = 160 MHz
B-Grade
I
DDINT
(mA)
1
CCLK = 140 MHz
Core Peripheral Core Peripheral
Activity Typ
1
1
Test conditions: V
DDINT
= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
AMB
= 25ºC.
Max
2
2
Test conditions: V
DDINT
= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
AMB
= 25ºC.
Ty p
1
Max
2
Ty p
1
Max
2
Ty p
1
Max
2
Power Down
3
3
PLL, Core, peripheral clocks, and CLKIN are disabled.
100 µA 600 µA 0 50 µA 100 µA 500 µA 0 50 µA
Idle 1
4
4
PLL is enabled and Core and peripheral clocks are disabled.
12581247
Idle 2
5
5
Core CLK is disabled and peripheral clock is enabled.
126070125562
Typical
6
6
All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence. 50% of the instructions are type 3 instructions.
184 210 60 70 165 185 55 62
Peak
7
7
All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear
address sequence.
215 240 60 70 195 210 55 62
I
DDINT
%Typical I
DDINT-TYPICAL
×()= %Idle I
DDINT-IDLE
×()%Power Down I
DDINT-PWRDWN
×()++