a DSP Microcomputer ADSP-2191M PERFORMANCE FEATURES 6.
ADSP-2191M INTEGRATION FEATURES 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-Bit Accumulators Unified Memory Space Allows Flexible Address Generation, Using Two Independent DAG Units Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Enhanced Interrupt Cont
ADSP-2191M GENERAL DESCRIPTION uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The functional block diagram on Page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter.
ADSP-2191M The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Boot memory space and I/O memory space also share the external buses.
ADSP-2191M Three programmable interval timers generate periodic interrupts. Each timer can be independently set to operate in one of three modes: pulsewidth register. A single status register supports all three timers. A bit in each timer’s configuration register enables or disables the corresponding timer independently of the others. • Pulse Waveform Generation mode Memory Architecture • Pulsewidth Count/Capture mode The ADSP-2191M DSP provides 64K words of on-chip SRAM memory.
ADSP-2191M the instruction provides an immediate 24-bit address value. The PC allows linear addressing of the full 24-bit address range. 8-bit I/O page (IOPG) register and a 10-bit immediate value supplied in the instruction. Both the ADSP-219x core and a Host (through the Host Port Interface) can access I/O memory space.
ADSP-2191M Table 2.
ADSP-2191M Host can directly access the DSP’s entire memory space map, boot memory space, and internal I/O space. To access the DSP’s internal memory space, a Host steals one cycle per access from the DSP. A Host access to the DSP’s external memory uses the external port interface and does not stall (or steal cycles from) the DSP’s core. Because a Host can access internal I/O memory space, a Host can control any of the DSP’s I/O mapped peripherals.
ADSP-2191M • Framing—each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulsewidths and early or late frame sync. During transfers, the SPI ports simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
ADSP-2191M Interface (SPI) Ports on Page 9 and Clock Signals on Page 11. Ten memory-mapped registers control operation of the Programmable Flag pins: • Flag Direction register Specifies the direction of each individual PFx pin as input or output. Power-Down Core Mode When the ADSP-2191M is in Power-Down Core mode, the DSP core clock is off, but the DSP retains the contents of the pipeline and keeps the PLL running. The peripheral bus keeps running, letting the peripherals receive data.
ADSP-2191M Clock Signals 1M⍀ The ADSP-2191M can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. If a crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors and a 1 MΩ shunt resistor connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer.
ADSP-2191M BMODE0 BMODE1 OPMODE Table 6.
ADSP-2191M Development Tools Because of synchronizer and arbitration delays, bus grants will be provided with a minimum of three peripheral clock delays. ADSP-2191M DSPs will respond to the bus grant by: The ADSP-2191M is supported with a complete set of software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other ADSP-219x DSPs, also fully emulates the ADSP-2191M.
ADSP-2191M In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-219x processor family. Hardware tools include ADSP-219x PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. As can be seen in Figure 4, there are two sets of signals on the header.
ADSP-2191M Additional Information 0.10" 0.15" Figure 7. JTAG Pod Connector Keep-Out Area Design-for-Emulation Circuit Information For details on target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.
ADSP-2191M Table 7.
ADSP-2191M Table 7. Pin Function Descriptions (continued) Pin Type Function TMR2–0 RXD TXD RESET I/O/T I O I TCK I TMS I TDI I TDO TRST O I EMU O VDDINT VDDEXT GND NC P P G Timer Output or Capture UART Serial Receive Data UART Serial Transmit Data Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at powerup.
ADSP-2191M SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter VDDINT Test Conditions VIH Internal (Core) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage VIL Low Level Input Voltage TAMB Ambient Operating Temperature VDDEXT @ VDDINT = max, VDDEXT = max @ VDDINT = min, VDDEXT = min K Grade (Commercial) B Grade (Industrial) Min Max Min Max Unit 2.37 2.63 2.37 2.63 V 2.97 3.6 2.97 3.6 V 2.0 VDDEXT +0.3 2.0 VDDEXT +0.3 V –0.3 +0.8 –0.3 +0.
ADSP-2191M ABSOLUTE MAXIMUM RATINGS VDDINT Internal (Core) Supply Voltage1 . . . –0.3 V to +3.0 V VDDEXT External (I/O) Supply Voltage . . . . –0.3 V to +4.6 V VIL–VIH Input Voltage . . . . . . . . . . –0.5 V to VDDEXT +0.5 V VOL–VOH Output Voltage Swing. . . –0.5 V to VDDEXT +0.5 V TSTORE Storage Temperature Range . . . . . .–65ºC to +150ºC TLEAD Lead Temperature of ST-144 (5 seconds) . . . . 185ºC 1Stresses greater than those listed above may cause permanent damage to the device.
ADSP-2191M TIMING SPECIFICATIONS This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, parameters cannot be added meaningfully to derive longer times.
ADSP-2191M Programmable Flags Cycle Timing Table 10 and Figure 9 describe Programmable Flag operations. Table 10. Programmable Flags Cycle Timing Parameter Min Switching Characteristics tDFO Flag Output Delay with Respect to CLKOUT tHFO Flag Output Hold After CLKOUT High Timing Requirement tHFI Flag Input Hold is Asynchronous Max Unit 7 6 ns ns 3 ns CLKOUT tDFO tHFO PF (OUTPUT) FLAG OUTPUT tHFI PF (INPUT) FLAG INPUT Figure 9.
ADSP-2191M External Port Write Cycle Timing Table 12 and Figure 11 describe external port write operations. The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access.
ADSP-2191M External Port Read Cycle Timing Table 13 and Figure 12 describe external port read operations. For additional information on the ACK signal, see the discussion on Page 22. Table 13.
ADSP-2191M External Port Bus Request and Grant Cycle Timing Table 14 and Figure 13 describe external port bus request and bus grant operations. Table 14.
ADSP-2191M Host Port ALE Mode Write Cycle Timing Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on Page 8. Table 15.
ADSP-2191M HCMS HIO MS tA LC SW tA LPW t CS A L tW C SW HALE t WC S tA LW HWR t H KW D t WH K S t WH K H HACK (ACK MODE ) HACK EACH BYTE tW H H tWH S HACK (READY MODE ) HACK FIRS T BY TE tA LA H t D WS tAA LS HAD15–0 HA16 t WD H ADDRE SS VALID DATA VALID DATA V ALI D START FIRST WORD FI RS T BY TE LAST BY TE ADDRESS V ALID S TART NEX T WORD Figure 14. Host Port ALE Mode Write Cycle Timing –26– REV.
ADSP-2191M Host Port ACC Mode Write Cycle Timing Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on Page 8. Table 16.
ADSP-2191M HCMS HIOMS tA L CS tC SA L tWC SW tWA L HALE tC SW tA LW tWC S t ALE W HWR tH K WD tH KW A L HACK (ACK MO DE) tWH K H tWS H KS tWH K S HACK EACH BYT E t WHH K H tW H H tWH S HACK (READY MO DE) HACK FI RST BYTE tWA D tA D W HAD15–0 HA16 tD WS t WD H ADDRESS VALID DATA VALID DATA VALID ADDRESS VALID START FIRST WORD FIRST BYTE LAST BYTE START NEXT WORD Figure 15. Host Port ACC Mode Write Cycle Timing –28– REV.
ADSP-2191M Host Port ALE Mode Read Cycle Timing Table 17 and Figure 16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on Page 8. Table 17.
ADSP-2191M HCMS HIO MS t ALC S tC S AL tR C S W HAL E tA LP W tR C S tAL R HRD t RH K S HACK (ACK MODE) t HK R D tR H K H HACK FOR EACH BYTE t RH H t RH S HA CK (READY MO DE) HACK FIRST BYTE tA L A H tA A L S HAD15–0 HA16 tR D H tR D D ADDRESS VALID DATA VALID DATA VALID ADDRESS VALID START FI RST WO RD FIRST BYTE LAST BYTE START NEXT WORD Figure 16. Host Port ALE Mode Read Cycle Timing –30– REV.
ADSP-2191M Host Port ACC Mode Read Cycle Timing Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on Page 8. Table 18.
ADSP-2191M HCMS HIO MS t ALC S tC S A L t RC S W HALE t WA L t t R CS tA LW HWR tC S R t ALE R HRD t HK W AL t H K RD t R H KS HACK (ACK MODE ) t R HK H t WSH K S HACK EACH BYTE t WH H KH tR H H t RHS HACK (READY MODE ) HACK FIRS T BY TE HAD15–0 HA16 t RDH t WA D tA D W tR D D ADDRE SS VALID DATA V ALID DATA V ALID ADDRE SS VALID START FI RS T WORD FIRS T BY TE L AST BY TE START NE XT WORD Figure 17. Host Port ACC Mode Read Cycle Timing –32– REV.
ADSP-2191M Serial Ports Table 19 and Figure 18 describe SPORT transmit and receive operations, while Figure 19 and Figure 20 describe SPORT Frame Sync operations. Table 19. Serial Ports1, 2 Parameter Min External Clock Timing Requirements TFS/RFS Setup Before TCLK/RCLK3 tSFSE tHFSE TFS/RFS Hold After TCLK/RCLK3 tSDRE Receive Data Setup Before RCLK3 tHDRE Receive Data Hold After RCLK3 tSCLKW TCLK/RCLK Width tSCLK TCLK/RCLK Period 4 4 1.5 4 0.
ADSP-2191M DATA RECEIVE-INTERNAL CLOCK DATA RECEIVE-EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DRIVE EDGE SAMPLE EDGE tSCLKIW tSCLKW RCLK RCLK tDFSE tHOFSE tSFSI tDFSE tHOFSE tHFSI RFS tSFSE tHFSE tSDRE tHDRE RFS tSDRI tHDRI DR DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
ADSP-2191M EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RCLK tHOSFSE/ I tSFSE/ I RFS tDDTE/ I tHDTE/ I tDTENLFSE DT 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK tHOSFSE/ I tSFSE / I TFS tDDTE / I tHDTE/ I tDTENLFSE 1ST BIT DT 2ND BIT tDDTLFSE Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.
ADSP-2191M Serial Peripheral Interface (SPI) Port—Master Timing Table 20 and Figure 21 describe SPI port master operations. Table 20.
ADSP-2191M Serial Peripheral Interface (SPI) Port—Slave Timing Table 21 and Figure 22 describe SPI port slave operations. Table 21.
ADSP-2191M Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 23 there is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
ADSP-2191M JTAG Test And Emulation Port Timing Table 22 and Figure 24 describe JTAG port operations. Table 22.
ADSP-2191M Output Drive Currents Figure 25 shows typical I-V characteristics for the output drivers of the ADSP-2191M. The curves represent the current drive capability of the output drivers as a function of output voltage. The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • Number of output pins that switch during each cycle (O) • The maximum frequency at which they can switch (f) • Their load capacitance (C) 60 VDDEXT = 3.
ADSP-2191M t DECAY output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 26). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. C L ∆V = --------------IL The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 26.
ADSP-2191M T AMB = T CASE – PD × θ CA OUTPUT DELAY OR HOLD – ns 30 Where: 20 • TAMB = Ambient temperature (measured near top surface of package) • PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). 10 • θCA = Value from Table 24. 0 • For the LQFP package: θJC = 0.96°C/W For the mini-BGA package: θJC = 8.4°C/W – 10 0 50 100 150 200 250 LOAD CAPACITANCE – pF Table 24. θCA Values Airflow (Linear Ft./Min.
ADSP-2191M 144-Lead LQFP Pinout Table 25 lists the LQFP pinout by signal name. Table 26 lists the LQFP pinout by pin. Table 25. 144-Lead LQFP Pins (Alphabetically by Signal) Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No.
ADSP-2191M Table 26. 144-Lead LQFP Pins (Numerically by Pin Number) Pin No. Signal Pin No. Signal Pin No. Signal Pin No.
ADSP-2191M 144-Lead Mini-BGA Pinout Table 27 lists the mini-BGA pinout by signal name. Table 28 lists the mini-BGA pinout by ball number. Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal) Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ADSP-2191M Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number) Ball No. Signal Ball No. Signal Ball No. Signal Ball No.
ADSP-2191M OUTLINE DIMENSIONS 144-Lead Metric Thin Plastic Quad Flatpack [LQFP] (ST-144) 22.00 BSC SQ 20.00 BSC SQ 109 144 108 1 PIN 1 INDICATOR 0.50 BSC TYP (LEAD PITCH) 0.27 0.22 TYP 0.17 SEATING PLANE 0.08 MAX (LEAD COPLANARITY) 0.15 0.05 0.75 0.60 0.45 1.45 1.40 1.35 73 36 72 37 1.60 MAX DETAIL A DETAIL A TOP VIEW (PINS DOWN) NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB. 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.
ADSP-2191M ORDERING GUIDE Part Number1, 2 Ambient Temperature Range Instruction Rate (MHz) Package Description Operating Voltage ADSP-2191MKST-160 ADSP-2191MBST-140 ADSP-2191MKCA-160 ADSP-2191MBCA-140 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 160 140 160 140 144-Lead LQFP 144-Lead LQFP 144-Ball Mini-BGA 144-Ball Mini-BGA 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2.5 Int./3.3 Ext. V 2CA = Plastic Thin Quad Flatpack (LQFP).
