Datasheet
REV. 0
–6–
ADSP-2188M
Common-Mode Pins
Pin Name # of Pins I/O Function
RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2 1 I Edge- or Level-Sensitive Interrupt Request
1
PF7 I/O Programmable I/O Pin
IRQL1 1 I Level-Sensitive Interrupt Requests
1
PF6 I/O Programmable I/O Pin
IRQL0 1 I Level-Sensitive Interrupt Requests
1
PF5 I/O Programmable I/O Pin
IRQE 1 I Edge-Sensitive Interrupt Requests
1
PF4 I/O Programmable I/O Pin
Mode D 1 I Mode Select Input—Checked Only During RESET
PF3 I/O Programmable I/O Pin During Normal Operation
Mode C 1 I Mode Select Input—Checked Only During RESET
PF2 I/O Programmable I/O Pin During Normal Operation
Mode B 1 I Mode Select Input—Checked Only During RESET
PF1 I/O Programmable I/O Pin During Normal Operation
Mode A 1 I Mode Select Input—Checked Only During RESET
PF0 I/O Programmable I/O Pin During Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO
2
PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
V
DDINT
2 I Internal V
DD
(2.75 V) Power (LQFP)
V
DDEXT
4 I External V
DD
(2.75 V or 3.3 V) Power (LQFP)
GND 10 I Ground (LQFP)
V
DDINT
4 I Internal V
DD
(2.75 V) Power (Mini-BGA)
V
DDEXT
7 I External V
DD
(2.75 V or 3.3 V) Power (Mini-BGA)
GND 20 I Ground (Mini-BGA)
EZ-Port 9 I/O For Emulation Use
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.