Datasheet

REV. 0
ADSP-2188M
–35–
Parameter Min Max Unit
IDMA Read, Short Read Cycle in Short Read Only Mode
1
Timing Requirements:
t
IKR
IACK Low before Start of Read
2
0ns
t
IRP
Duration of Read
3
10 ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
2
10 ns
t
IKDH
IAD15–0 Previous Data Hold after End of Read
3
0ns
t
IKDD
IAD15–0 Previous Data Disabled after End of Read
3
10 ns
t
IRDE
IAD15–0 Previous Data Enabled after Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid after Start of Read 10 ns
NOTES
1
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the
register or by an external host writing to the register. Disabled by default.
2
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3
End of Read = IS High or IRD High.
t
IRP
t
IKR
PREVIOUS
DATA
t
IKHR
t
IRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
Figure 32. IDMA Read, Short Read Only Cycle