Datasheet

REV. 0
–34–
ADSP-2188M
Parameter Min Max Unit
IDMA Read, Short Read Cycle
1, 2
Timing Requirements:
t
IKR
IACK Low before Start of Read
3
0ns
t
IRP1
Duration of Read (DM/PM1)
4
10 2t
CK
– 5ns
t
IRP2
Duration of Read (PM2)
5
10 t
CK
– 5ns
Switching Characteristics:
t
IKHR
IACK High after Start of Read
3
10 ns
t
IKDH
IAD15–0 Data Hold after End of Read
6
0ns
t
IKDD
IAD15–0 Data Disabled after End of Read
6
10 ns
t
IRDE
IAD15–0 Previous Data Enabled after Start of Read 0 ns
t
IRDV
IAD15–0 Previous Data Valid after Start of Read 10 ns
NOTES
1
Short Read Only must be disabled in the IDMA Overlay memory mapped register.
2
Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3
Start of Read = IS Low and IRD Low.
4
DM Read or first half of PM Read.
5
Second half of PM Read.
6
End of Read = IS High or IRD High.
t
IRP
t
IKR
PREVIOUS
DATA
t
IKHR
t
IRDV
t
IKDD
t
IRDE
t
IKDH
IAD15–0
IACK
IS
IRD
Figure 31. IDMA Read, Short Read Cycle